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參數(shù)資料
| 型號： | ISL6522ACRZ-T |
| 廠商： | INTERSIL CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | Buck and Synchronous Rectifier Pulse-Width Modulator (PWM) Controller |
| 中文描述： | SWITCHING CONTROLLER, 1000 kHz SWITCHING FREQ-MAX, PQCC16 |
| 封裝： | 5 X 5 MM, ROHS COMPLIANT, PLASTIC, MO-220VHHB, QFN-16 |
| 文件頁數(shù)： | 10/13頁 |
| 文件大?。?/td> | 441K |
| 代理商： | ISL6522ACRZ-T |
10
FN9122.2
April 13, 2005
should be at least 1.25 times greater than the maximum
input voltage and a voltage rating of 1.5 times is a
conservative guideline. The RMS current rating requirement
for the input capacitor of a buck regulator is approximately
1/2 the DC load current.
For a through-hole design, several electrolytic capacitors
(Panasonic HFQ series or Nichicon PL series or Sanyo MV-GX
or equivalent) may be needed. For surface mount designs,
solid tantalum capacitors can be used, but caution must be
exercised with regard to the capacitor surge current rating.
These capacitors must be capable of handling the surge-
current at power-up. The TPS series available from AVX, and
the 593D series from Sprague are both surge current tested.
MOSFET Selection/Considerations
The ISL6522A requires two N-Channel power MOSFETs.
These should be selected based upon r
DS(ON)
, gate supply
requirements, and thermal management requirements.
In high-current applications, the MOSFET power dissipation,
package selection and heatsink are the dominant design
factors. The power dissipation includes two loss
components; conduction loss and switching loss. The
conduction losses are the largest component of power
dissipation for both the upper and the lower MOSFETs.
These losses are distributed between the two MOSFETs
according to duty factor. The switching losses seen when
sourcing current will be different from the switching losses seen
when sinking current. When sourcing current, the upper
MOSFET realizes most of the switching losses. The lower
switch realizes most of the switching losses when the converter
is sinking current (see the equations below).
Losses while Sourcing Current
Io
2
r
DS ON
)
+
=
These equations assume linear voltage-current transitions and
do not adequately model power loss due the reverse-recovery
of the upper and lower MOSFET’s body diode. The
gate-charge losses are dissipated by the ISL6522A and do not
heat the MOSFETs. However, large gate-charge increases the
switching interval, t
SW
which increases the upper MOSFET
switching losses. Ensure that both MOSFETs are within their
maximum junction temperature at high ambient temperature by
calculating the temperature rise according to package thermal-
resistance specifications. A separate heatsink may be
necessary depending upon MOSFET power, package type,
ambient temperature and air flow.
Standard-gate MOSFETs are normally recommended for
use with the ISL6522A. However, logic-level gate MOSFETs
can be used under special circumstances. The input voltage,
upper gate drive level, and the MOSFETs absolute gate-to-
source voltage rating determine whether logic-level
MOSFETs are appropriate.
Figure 9 shows the upper gate drive (BOOT pin) supplied by
a bootstrap circuit from V
CC
. The boot capacitor, C
BOOT
develops a floating supply voltage referenced to the PHASE
pin. This supply is refreshed each cycle to a voltage of V
CC
less the boot diode drop (V
D
) when the lower MOSFET, Q2
turns on. A logic-level MOSFET can only be used for Q1 if
the MOSFETs absolute gate-to-source voltage rating
exceeds the maximum voltage applied to V
CC
. For Q2, a
logic-level MOSFET can be used if its absolute gate-to-
source voltage rating exceeds the maximum voltage applied
to PVCC.
D
BOOT
Figure 10 shows the upper gate drive supplied by a direct
connection to V
CC
. This option should only be used in
converter systems where the main input voltage is +5V
DC
or
less. The peak upper gate-to-source voltage is approximately
P
LOWER
= Io
2
x r
DS(ON)
x (1 - D)
Where: D is the duty cycle = V
OUT
/ V
IN
,
t
SW
is the switching interval, and
F
S
is the switching frequency.
Losses while Sinking Current
P
UPPER
= Io
2
x r
DS(ON)
x D
P
LOWER
Io
2
r
DS ON
(
)
×
1
D
–
(
)
×
1
V
IN
×
t
SW
F
S
×
×
+
=
P
UPPER
×
D
×
1
V
IN
×
t
SW
F
S
×
×
+12V
PGND
ISL6522A
GND
LGATE
UGATE
PHASE
BOOT
VCC
+5V OR +12V
FIGURE 9. UPPER GATE DRIVE - BOOTSTRAP OPTION
NOTE:
V
G-S
V
CC
- V
D
NOTE:
V
G-S
≈
PVCC
C
BOOT
Q1
Q2
PVCC
+5V
OR +12V
D2
+
-
V
D
+
-
+12V
PGND
LGATE
UGATE
PHASE
BOOT
VCC
+5V OR LESS
FIGURE 10. UPPER GATE DRIVE - DIRECT V
CC
DRIVE OPTION
NOTE:
V
G-S
≈
V
CC
- 5V
NOTE:
V
G-S
≈
PVCC
Q1
Q2
PVCC
+5V
OR +12V
D2
ISL6522A
GND
+
-
ISL6522A
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