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參數(shù)資料
| 型號： | ISL6521CBZ-T |
| 廠商： | INTERSIL CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | Adjustable Precision Shunt Regulator 5-SOT-23 0 to 70 |
| 中文描述： | SWITCHING CONTROLLER, 325 kHz SWITCHING FREQ-MAX, PDSO16 |
| 封裝： | GREEN, PLASTIC, MS-012-AC, SOIC-16 |
| 文件頁數(shù)： | 6/13頁 |
| 文件大?。?/td> | 639K |
| 代理商： | ISL6521CBZ-T |
6
the clamped error amplifier output voltage. As the internal
soft-start voltage increases, the pulse-width on the PHASE
pin increases to reach its steady-state duty cycle at time T2.
Also at time T2, the error amplifier references of the linear
controllers, ramp to their final value bringing all outputs
within regulation limits.
Overcurrent Protection
All outputs are protected against excessive overcurrents.
The PWM controller uses the upper MOSFET’s
on-resistance, r
DS(ON)
to monitor the current for protection
against a shorted output. All linear controllers monitor their
respective FB pins for undervoltage events to protect against
excessive currents.
A sustained overload (undervoltage on linears or overcurrent
on the PWM) on any output results in an independent
shutdown of the respective output, followed by subsequent
individual re-start attempts performed at an interval equivalent
to 3 soft-start intervals. Figure 2 describes the protection
feature. At time T0, an overcurrent event sensed across the
switching regulator’s upper MOSFET (r
DS(ON)
sensing)
triggers a shutdown of the V
OUT1
output. As a result, its
internal soft-start initiates a number of soft-start cycles. After a
three-cycle wait, the fourth soft-start initiates a ramp-up
attempt of the failed output, at time T2, bringing the output in
regulation at time T4.
To exemplify a UV event on one of the linears, at time T1,
the clock regulator (V
OUT2
) is also subjected to an
overcurrent event, resulting in a UV condition. Similarly, after
three soft-start periods, the fourth cycle initiates a ramp-up of
this linear output at time T3. One soft-start period after T3,
the linear output is within regulation limits. UV glitches less
than 1
μ
s (typically) in duration are ignored.
Overcurrent protection is performed on the synchronous
switching regulator on a cycle-by-cycle basis. OC monitoring
is active as long as the regulator is operational. Since the
overcurrent protection on the linear regulators is performed
through undervoltage monitoring at the feedback pins (FB2,
FB3, and FB4), this feature is activated approximately 25%
into the soft-start interval (see Figure 2).
A resistor (R
OCSET
) programs the overcurrent trip level for
the PWM converter. As shown in Figure 3, the internal
40
μ
A current sink (I
OCSET
) develops a voltage across
R
OCSET
(V
SET
) that is referenced to V
IN
. The DRIVE
signal enables the overcurrent comparator (OCC). When
the voltage across the upper MOSFET (V
DS(ON)
) exceeds
V
SET
the overcurrent comparator trips to set the
overcurrent latch. Both V
SET
and V
DS(ON)
are referenced
to V
IN
and a small capacitor across R
OCSET
helps V
OCSET
track the variations of V
IN
due to MOSFET switching. The
overcurrent function will trip at a peak inductor current
(I
PEAK)
determined by:
I
DS ON
(
)
FIGURE 1. SOFT-START INTERVAL
0V
0V
TIME
(0.5V/DIV)
V
OUT4
(3.3V)
V
OUT1
(1.5V)
T1
T2
T0
(1V/DIV)
V
OUT3
(1.8V)
V
OUT2
(2.5V)
+5V
FIGURE 2. OVERCURRENT/UNDERVOLTAGE PROTECTION
RESPONSE
0V
TIME
(0.5V/DIV.)
V
OUT3
(1.8V)
V
OUT2
(2.5V)
T1
T2
T3
T0
V
OUT4
(3.3V)
V
OUT1
(1.5V)
UV MONITORING
INACTIVE
SOFT-START
FUNCTION
ACTIVE
T4
V
OUT2
V
OUT1
I
PEAK
=
R
OCSET
×
-------------r
ISL6521
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