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參數(shù)資料
| 型號(hào)： | ISL6520ACB |
| 廠商： | INTERSIL CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | Adjustable Precision Shunt Regulator 3-SOT-23 -40 to 125 |
| 中文描述： | SWITCHING CONTROLLER, 340 kHz SWITCHING FREQ-MAX, PDSO8 |
| 封裝： | PLASTIC, MS-012-AA, SOIC-8 |
| 文件頁數(shù)： | 5/10頁 |
| 文件大?。?/td> | 353K |
| 代理商： | ISL6520ACB |
5
FN9083.2
January 20, 2005
rail, which supplies the bias voltage to the ISL6520B. If there
is nowhere for this current to go, such as to other distributed
loads on the V
CC
rail, through a voltage limiting protection
device, or other methods, the capacitance on the V
CC
bus
will absorb the current. This situation will allow voltage level
of the V
CC
rail to increase. If the voltage level of the rail is
boosted to a level that exceeds the maximum voltage rating
of the ISL6520B, then the IC will experience an irreversible
failure and the converter will no longer be operational.
Ensuring that there is a path for the current to follow other
than the capacitance on the rail will prevent this failure mode.
Application Guidelines
Layout Considerations
As in any high frequency switching converter, layout is very
important. Switching current from one power device to another
can generate voltage transients across the impedances of the
interconnecting bond wires and circuit traces. These
interconnecting impedances should be minimized by using
wide, short printed circuit traces. The critical components
should be located as close together as possible, using ground
plane construction or single point grounding.
Figure 2 shows the critical power components of the converter.
To minimize the voltage overshoot, the interconnecting wires
indicated by heavy lines should be part of a ground or power
plane in a printed circuit board. The components shown in
Figure 2 should be located as close together as possible.
Please note that the capacitors C
IN
and C
O
may each
represent numerous physical capacitors. Locate the
ISL6520B
within 3 inches of the MOSFETs, Q
1
and Q
2
. The circuit traces
for the MOSFETs’ gate and source connections from the
ISL6520B must be sized to handle up to 1A peak current.
Figure 3 shows the circuit traces that require additional
layout consideration. Use single point and ground plane
construction for the circuits shown. Minimize any leakage
current paths on the COMP/SD pin and locate the resistor,
R
OSCET
close to the COMP/SD pin because the internal
current source is only 20
μ
A. Provide local V
CC
decoupling
between VCC and GND pins. Locate the capacitor, C
BOOT
as close as practical to the BOOT and PHASE pins. All
components used for feedback compensation should be
located as close to the IC a practical.
Feedback Compensation
Figure 4 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(V
OUT
) is regulated to the Reference voltage level. The
error amplifier (Error Amp) output (V
E/A
) is compared with
the oscillator (OSC) triangular wave to provide a
pulse-width modulated (PWM) wave with an amplitude of
V
IN
at the PHASE node. The PWM wave is smoothed by the
output filter (L
O
and C
O
).
The modulator transfer function is the small-signal transfer
function of V
OUT
/V
E/A
. This function is dominated by a DC
Gain and the output filter (L
O
and C
O
), with a double pole
L
O
C
O
LGATE
UGATE
PHASE
Q
1
Q
2
V
IN
V
OUT
RETURN
ISL6520B
C
IN
L
FIGURE 2. PRINTED CIRCUIT BOARD POWER AND
GROUND PLANES OR ISLANDS
FIGURE 3. PRINTED CIRCUIT BOARD SMALL SIGNAL
LAYOUT GUIDELINES
+5V
ISL6520B
GND
VCC
BOOT
D
1
L
O
C
O
V
OUT
L
Q
1
Q
2
PHASE
+V
IN
C
BOOT
C
VCC
FIGURE 4. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
V
OUT
REFERENCE
L
O
C
O
ESR
V
IN
V
OSC
ERROR
AMP
PWM
DRIVER
(PARASITIC)
Z
FB
+
-
REFERENCE
R
1
R
3
R
2
C
3
C
2
C
1
COMP/SD
V
OUT
FB
Z
FB
ISL6520B
Z
IN
COMPARATOR
DRIVER
DETAILED COMPENSATION COMPONENTS
PHASE
V
E/A
+
-
+
-
Z
IN
OSC
ISL6520B
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