參數(shù)資料
型號(hào): ISL6506BCB
廠商: INTERSIL CORP
元件分類: 電源管理
英文描述: Adjustable Precision Shunt Regulator 8-SOIC -40 to 125
中文描述: 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO8
封裝: 0.150 INCH, PLASTIC, SOIC-8
文件頁(yè)數(shù): 5/8頁(yè)
文件大?。?/td> 271K
代理商: ISL6506BCB
5
Soft-Start
Figures 3 and 4 show the soft-start sequence for the typical
application start-up into a sleep state. At time T0, 5V
SB
(bias) is applied to the circuit. At time T1, the 5V
SB
surpasses POR level. Time T2, one soft start interval after
T1, denotes the initiation of soft start. The 3.3V
DUAL
rail is
brought up through the internal standby LDO through an
internal digital soft start function. Figure 4 shows the 5V
DUAL
rail initiating a soft start at time T2 as well. The ISL6506A will
draw 7.5
μ
A into the 5VDLSB for a duration of one soft start
period. This current will enhance the P-MOSFET (Q
2
, refer
to Typical Application Schematic) in a controlled manner. At
time T3, the 3.3V
DUAL
is in regulation and the 5VDLSB pin
is pulled down to ground. If the 5V
DUAL
rail has not reached
the level of the 5V
SB
rail by time T3, then the rail will
experience a sudden step as the P-MOSFET gate is fully
enhanced. The soft start profile of the 5VDUAL may be
altered by placing a capacitor between the gate and drain of
the P-MOSFET. Adding this capacitor will increase the gate
capacitance and slow down the start of the 5V
DUAL
rail.
At time T4, the system has transitioned into S0 state and the
ATX supplies have begun to ramp up. With the ISL6506/B
(Figure 3), the 5V
DUAL
rail will begin to ramp up from the
5V
ATX
rail through the body diode of the N-MOSFET (Q
3
).
The ISL6506A will already have the 5V
DUAL
rail in
regulation (Figure 4). At time T5, the 12V
ATX
rail has
surpassed the 12V POR level. Time T6 is three soft start
cycles after the 12V POR level has been surpassed. At time
T6, three events occur simultaneously. The DLA pin is forced
to a high impedance state which allows the 12V rail to
enhance the two N-MOSFETs (Q
1
and Q
3
) that connect the
ATX rails to the 3.3V
DUAL
and 5V
DUAL
rails. The 5VDLSB
pin is forced to a high impedance state which will turn the
P-MOSFET (Q
2
) off. Finally, the internal LDO which regulates
the 3.3V
AUX
rail in sleep states in put in standby mode.
Sleep to Wake State Transitions
Figures 3 and 4, starting at time T4, depict the transitions
from sleep states to the S0 wake state. Figure 3 shows the
transition of the ISL6506/B from the S4/S5 state to the S0
state. Figure 4 shows how the ISL6506/B will transition from
the S3 sleep state into S0 state. Figure 3 also shows how
the ISL6506A transitions from either S3 or S4/S5 in the S0
state. For all transitions, T4 depicts the system transition into
the S0 state. Here, the ATX supplies are enabled and begin
to ramp up. At time T5, the 12V
ATX
rail has exceeded the
POR threshold for the ISL6506/B and ISL6506A. Three soft
start periods after time T5, at time T6, three events occur
FIGURE 2. 5V
DUAL
AND 3.3V
AUX
TIMING DIAGRAM;
ISL6506A
5VSB
3.3V, 5V, 12V
S3
S5
5VDLSB
DLA
3V3DL
5VDL
0V
TIME
5VSB
(1V/DIV)
FIGURE 3. ISL6506 and ISL6506B SOFT-START INTERVAL
IN S4/S5 STATE AND S5 TO S0 TRANSITION
12VATX (2V/DIV)
5VATX (1V/DIV)
3.3VATX (1V/DIV)
5VDUAL
(1V/DIV)
3.3VDUAL
(2V/DIV)
T1
T2
T3
T0
T5
T4
T6
DLA
(10V/DIV)
FIGURE 4. SOFT START INTERVAL FOR ISL6506A IN S4/S5
AND S5 TO S0 TRANSITION FOR ISL6506A AND
S3 TO S0 TRANSITION FOR ISL6506/A/B
0V
TIME
T1
T2
T3
T0
T5
T4
T6
5VDLSB
(5V/DIV)
5VSB
(1V/DIV)
5VDUAL
(1V/DIV)
3.3VDUAL
(2V/DIV)
DLA
(10V/DIV)
12VATX (2V/DIV)
5VATX (1V/DIV)
3.3VATX (1V/DIV)
ISL6506, ISL6506A, ISL6506B
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