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參數(shù)資料
| 型號(hào)： | ISL6455 |
| 廠商： | Intersil Corporation |
| 英文描述： | Triple Output Regulator with Single Synchronous Buck and Dual LDO(帶單同步降壓和雙LDO的三路輸出調(diào)節(jié)器) |
| 中文描述： | 三單和雙同步降壓穩(wěn)壓器LDO輸出（帶單同步降壓和雙穩(wěn)壓器的三路輸出調(diào)節(jié)器） |
| 文件頁數(shù)： | 8/12頁 |
| 文件大?。?/td> | 320K |
| 代理商： | ISL6455 |
8
FN9196.0
December 21, 2005
Pin Descriptions
PVCC
- Positive supply for the power (internal FET) stage of
the PWM section.
SGND
- Analog ground for the PWM. All internal control
circuits are referenced to this pin.
EN
- The PWM controller is enabled when this pin is HIGH,
and disabled when the pin is pulled LOW. It is a CMOS logic-
level input (referenced to V
IN
).
V
IN
_LDO
- This is the input voltage pin for LDO1 and LDO2.
EN_LDO
- LDO1 and LDO2 are enabled when this pin is
HIGH, and disabled when the pin is pulled LOW. It is a
CMOS logic-level input (referenced to V
IN
).
CT
- Timing capacitor pin to set the 25ms minimum pulse
width for the RESET signal.
RESET
- This pin is the output of the reset supervisory
circuit, which monitors VIN_PWM. The IC asserts a RESET
signal whenever the supply voltage drops below a preset
threshold. It is kept asserted for a minimum of 25ms after
V
CC
(V
IN
) has risen above the reset threshold. The output is
push-pull. The device will continue to operate until V
IN
drops
below the UVLO threshold.
When EN = LOW then RESET = HIGH and the moment EN
is made HIGH the RESET will pulse LOW for a period of
25ms minimum (VIN > Reset threshold). If VIN < reset
threshold then it will switch low and stay low for a period of
25ms after VIN_PWM crosses the reset threshold.
PG_LDO
- This is a high impedance open drain output that
provides the status of both LDOs. When either of the outputs
are out of regulation, PG_LDO goes LOW.
CC1
- This is the compensation capacitor connection for
LDO1. Connect a 0.033μF capacitor from CC1 to
GND_LDO.
CC2
- This is the compensation capacitor connection for
LDO2. Connect a 0.033μF capacitor from CC2 to
GND_LDO.
V
OUT2
- This pin is the output of LDO2. Bypass with a
minimum 2.2μF, low ESR capacitor to GND_LDO for stable
operation.
GND_LDO
- Ground pin for LDO1 and LDO2.
V
OUT1
- This pin is the output of LDO1. Bypass with a
minimum 2.2μF, low ESR capacitor to GND_LDO for stable
operation.
PGND
- Power ground for the PWM controller stage.
V
OUT
- This I/O pin senses the output voltage of the PWM
converter for the purpose of detecting the over and
undervoltage conditions.
PG_PWM
- This pin is an active pull-up/pull-down able to
source/sink 1mA (min.) at 0.4V from V
IN
/SGND. This output
is HIGH when V
OUT
is within ±8% (typical).
FB_LDO1 and FB_LDO2 -
These pins are used to set the
LDO output with the proper selection of resistors. i.e. Ra and
Rb for LDO1 and Rc and Rd for LDO2. Resistors should be
chosen to provide a minimum current of 200μA load for each
LDO output.
LX
- The LX pin is the switching node of synchronous buck
converter, connected internally at the junction point of the
upper MOSFET source and lower MOSFET drain. Connect
this pin to the output inductor.
V
IN
- This pin is the power supply for the PWM controller
stage and must be closely decoupled to ground.
SYNC
- This is the external clock synchronization input. The
device can be synchronized to 500kHz to 1MHz switching
frequency. If unused then it should be tied to GND or VCC
GND
- Tie this pin to the ground plane with a low impedance,
shortest possible path.
FB_PWM
- This is used to set the value of the output voltage
of the PWM with external resistors Re and Rf.
Functional Description
The ISL6455 is a 3-in-1 multi-output regulator designed for
FPGA and wireless chipset power applications. The device
integrates a single synchronous buck regulator with dual
LDOs. The PWM output can be set by choosing appropriate
values for Re and Rf. At a setting of 1.8V the synchronous
buck regulator provides for an efficiency greater than 92%.
The LDO1 can be set with resistor pair Rc and Rd. The
LDO2 can be set with the resistor pair Ra and Rb.
Undervoltage lock-out (UVLO) prevents the converter from
turning on when the input voltage is less than 2.6V typical.
Additional blocks include output overcurrent protection,
thermal sensor, PGOOD detectors, RESET function and
shutdown logic.
Synchronous Buck Regulator
The synchronous buck regulator with integrated N- and
P-channel power MOSFETs and external voltage setting
resistors provides for adjustable voltages from the PWM.
Synchronous rectification with internal MOSFETs is used to
achieve higher efficiency and reduced number of external
components. Operating frequency is typically 750kHz
allowing the use of smaller inductor and capacitor values.
The device can be synchronized to an external clock signal
in the range of 500kHz to 1MHz. The PG_PWM output
indicates loss of regulation on PWM output.
The PWM architecture uses a peak current mode control
scheme with internal slope compensation. At the beginning
of each clock cycle, the high side P-channel MOSFET is
turned on. The current in the inductor ramps up and is
ISL6455, ISL6455A
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| ISL6455AEVAL1Z | 功能描述:EVALUATION BOARD FOR ISL6455A RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估板 - DC/DC 與 AC/DC（離線）SMPS 系列:- 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:True Shutdown™ 主要目的:DC/DC，步升 輸出及類型:1，非隔離 功率 - 輸出:- 輸出電壓:- 電流 - 輸出:1A 輸入電壓:2.5 V ~ 5.5 V 穩(wěn)壓器拓?fù)浣Y(jié)構(gòu):升壓 頻率 - 開關(guān):3MHz 板類型:完全填充 已供物品:板 已用 IC / 零件:MAX8969 |
| ISL6455AIRZ | 功能描述:電流型 PWM 控制器 SYNC BUCK PWMG DLLDO 5V INP 24LD 4X4 RoHS:否 制造商:Texas Instruments 開關(guān)頻率:27 KHz 上升時(shí)間: 下降時(shí)間: 工作電源電壓:6 V to 15 V 工作電源電流:1.5 mA 輸出端數(shù)量:1 最大工作溫度:+ 105 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSSOP-14 |
| ISL6455AIRZS2698 | 功能描述:IC REG TRPL SYNC DUAL LDO 24-QFN RoHS:是 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - 專用型 系列:- 標(biāo)準(zhǔn)包裝:43 系列:- 應(yīng)用:控制器，Intel VR11 輸入電壓:5 V ~ 12 V 輸出數(shù):1 輸出電壓:0.5 V ~ 1.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:48-QFN（7x7） 包裝:管件 |
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