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參數(shù)資料
| 型號： | ISL6441 |
| 廠商： | Intersil Corporation |
| 英文描述： | 1.4MHz Dual, Out-of-Phase, Step-Down PWM and Single Linear Controller(1.4MHz兩路,異相，降壓型PWM，外加一路線性控制器) |
| 中文描述： | 1.4MHz的雙通道，外的階段，降壓型PWM和線性控制器單（1.4MHz的兩路，異相，降壓型脈寬調(diào)制，外加一路線性控制器） |
| 文件頁數(shù)： | 12/18頁 |
| 文件大?。?/td> | 380K |
| 代理商： | ISL6441 |
12
FN9197.1
October 4, 2005
Input Voltage Range
The ISL6441 is designed to operate from input supplies
ranging from 4.5V to 24V. However, the input voltage range
can be effectively limited by the available maximum duty
cycle (D
MAX
= 71%).
where,
Vd1 = Sum of the parasitic voltage drops in the inductor
discharge path, including the lower FET, inductor and PC
board.
Vd2 = Sum of the voltage drops in the charging path,
including the upper FET, inductor and PC board resistances.
The maximum input voltage and minimum output voltage is
limited by the minimum on-time (t
ON(min)
).
where, t
ON(min)
= 30ns
Gate Control Logic
The gate control logic translates generated PWM signals
into gate drive signals providing amplification, level shifting
and shoot-through protection. The gate drivers have some
circuitry that helps optimize the IC’s performance over a
wide range of operational conditions. As MOSFET switching
times can vary dramatically from type to type and with input
voltage, the gate control logic provides adaptive dead time
by monitoring real gate waveforms of both the upper and the
lower MOSFETs. Shoot-through control logic provides a
20ns deadtime to ensure that both the upper and lower
MOSFETs will not turn on simultaneously and cause a shoot-
through condition.
Gate Drivers
The low-side gate driver is supplied from VCC_5V and
provides a peak sink/source current of 400mA. The high-
side gate driver is also capable of 400mA current. Gate-drive
voltages for the upper N-Channel MOSFET are generated
by the flying capacitor boot circuit. A boot capacitor
connected from the BOOT pin to the PHASE node provides
power to the high side MOSFET driver. To limit the peak
current in the IC, an external resistor may be placed
between the UGATE pin and the gate of the external
MOSFET. This small series resistor also damps any
oscillations caused by the resonant tank of the parasitic
inductances in the traces of the board and the FET’s input
capacitance.
At start-up the low-side MOSFET turns on and forces
PHASE to ground in order to charge the BOOT capacitor to
5V. After the low-side MOSFET turns off, the high-side
MOSFET is turned on by closing an internal switch between
BOOT and UGATE. This provides the necessary gate-to-
source voltage to turn on the upper MOSFET, an action that
boosts the 5V gate drive signal above VIN. The current
required to drive the upper MOSFET is drawn from the
internal 5V regulator.
Protection Circuits
The converter output is monitored and protected against
overload, short circuit and undervoltage conditions. A
sustained overload on the output sets the PGOOD low and
initiates hiccup mode.
Overcurrent Protection
Cycle by cycle current limiting scheme is implemented as
below. Both PWM controllers use the lower MOSFET’s on-
resistance, r
DS(ON)
, to monitor the current in the converter.
The sensed voltage drop is compared with a threshold set by
a resistor connected from the OCSETx pin to ground.
where, I
OC
is the desired overcurrent protection threshold,
and R
CS
is a value of the current sense resistor connected
to the ISENx pin. If the lower MOSFET current exceeds the
over-current threshold, a pulse skipping circuit is activated.
Figure 16 shows the inductor current, output voltage, and the
PHASE node voltage just as an overcurrent trip occurs. The
upper MOSFET will not be turned on as long as the sensed
current is higher than the threshold value. This limits the
current supplied by the DC voltage source. If an overcurrent
is detected for 2 consecutive clock cycles then the IC enters
a hiccup mode by turning off the gate drivers and entering
into soft-start. The IC will cycle 2 times through soft-start
before trying to restart. The IC will continue to cycle through
soft-start until the overcurrent condition is removed.
Figure 17 shows this behavior.
V
IN min
)
V
--------------------------------
V
+
V
d2
V
d1
–
+
=
V
IN max
)
V
t
ON min
)
1.4MHz
---------------------------------------------------
≤
BOOT
UGATE
PHASE
VCC_5V
VIN
ISL6441
FIGURE 15.
R
OCSET
7
( )
R
I
OC
R
DS on
)
)
------------------------------------------
=
ISL6441
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