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參數(shù)資料
| 型號(hào)： | ISL6440ACB |
| 廠商： | INTERSIL CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | Advanced PWM and Triple Linear Power Controller for Gateway Applications |
| 中文描述： | SWITCHING CONTROLLER, 1000 kHz SWITCHING FREQ-MAX, PDSO28 |
| 封裝： | PLASTIC, MS-013AE, SOIC-28 |
| 文件頁數(shù)： | 12/16頁 |
| 文件大小： | 749K |
| 代理商： | ISL6440ACB |
12
R3, C1, C2, and C3) in Figure 7. Use these guidelines for
locating the poles and zeros of the compensation network:
1. Pick gain (R2/R1) for desired converter bandwidth
2. Place first
zero below filter’s double pole (~75% F
LC
)
3. Place second zero at filter’s double pole
4. Place first pole at the ESR zero
5. Place second pole at half the switching frequency
6. Check gain against error amplifier’s open-loop gain
7. Estimate phase margin - repeat if necessary
Figure 9 shows an asymptotic plot of the DC-DC converter’s
gain vs. frequency. The actual modulator gain has a high gain
peak dependent on the quality factor (Q) of the output filter,
which is not shown in Figure 8. Using the above guidelines
should yield a compensation gain similar to the curve plotted.
Check the compensation gain at F
P2
with the capabilities of the
error amplifier. The closed loop gain is constructed on the log-
log graph of Figure 9 by adding the modulator gain (in dB) to
the compensation gain (in dB). This is equivalent to multiplying
the modulator transfer function to the compensation transfer
function and plotting the gain.
The compensation gain uses external impedance networks
Z
FB
and Z
IN
to provide a stable, high bandwidth (BW) overall
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45
degrees. Include worst-case component variations when
determining phase margin.
Compensation Break Frequency Equations
FIGURE 7. PRINTED CIRCUIT BOARD POWER PLANES
AND ISLANDS
V
OUT1
Q1
L
OUT1
Q2
Q3
Q4
C
SS
+12V
C
VCC
VIA CONNECTION TO GROUND PLANE
ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT PLANE LAYER
C
OUT1
CR1
ISL6440A
C
IN
C
OUT2
V
OUT2
V
OUT3
+5V
IN
SS
PGND
LGATE1
UGATE1
PHASE1
DRIVE3
KEY
GND
OCSET1
VCC
DRIVE2
R
OCSET1
C
OCSET1
L
V
OUT4
DRIVE4
+3.3V
IN
L
IN
Q5
C
OUT3
C
OUT4
L
L
L
+3.3V
IN
FIGURE 8. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
V
OUT
OSC
REFERENCE
L
O
C
O
ESR
V
IN
V
OSC
ERROR
AMP
PWM
COMP
DRIVER
(PARASITIC)
Z
FB
+
-
DACOUT
R1
R3
R2
C3
C2
C1
COMP
V
OUT
FB
Z
FB
ISL6440A
Z
IN
DRIVER
DETAILED COMPENSATION COMPONENTS
PHASE
V
E/A
+
-
+
-
Z
IN
F
Z1
-----------------------------------
=
F
Z2
R3
)
C3
×
------------------------+
=
F
P1
2
π
R
2
--------+
×
×
------------------------------------------------------
=
F
P2
-----------------------------------
=
FIGURE 9. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
100
80
60
40
20
0
-20
-40
-60
F
P1
F
Z2
10M
1M
100K
10K
1K
100
10
OPEN LOOP
ERROR AMP GAIN
F
Z1
F
P2
F
LC
F
ESR
COMPENSATION
GAIN
G
FREQUENCY (Hz)
MODULATOR
GAIN
CLOSED LOOP
GAIN
20
VPP
log
20
R1
log
ISL6440A
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| ISL6440ACB WAF | 制造商:Harris Corporation 功能描述: |
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| ISL6440EVAL1 | 制造商:Intersil Corporation 功能描述:EVAL BD FOR ISL6440 - Bulk |
| ISL6440EVAL1Z | 功能描述:EVALUATION BOARD FOR ISL6440 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估板 - DC/DC 與 AC/DC（離線）SMPS 系列:- 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:True Shutdown™ 主要目的:DC/DC，步升 輸出及類型:1，非隔離 功率 - 輸出:- 輸出電壓:- 電流 - 輸出:1A 輸入電壓:2.5 V ~ 5.5 V 穩(wěn)壓器拓?fù)浣Y(jié)構(gòu):升壓 頻率 - 開關(guān):3MHz 板類型:完全填充 已供物品:板 已用 IC / 零件:MAX8969 |
| ISL6440IA | 功能描述:IC REG CTRLR BUCK PWM CM 24-QSOP RoHS:否 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 切換控制器 系列:- 標(biāo)準(zhǔn)包裝:4,000 系列:- PWM 型:電壓模式 輸出數(shù):1 頻率 - 最大:1.5MHz 占空比:66.7% 電源電壓:4.75 V ~ 5.25 V 降壓:是 升壓:無 回掃:無 反相:無 倍增器:無 除法器:無 Cuk:無 隔離:無 工作溫度:-40°C ~ 85°C 封裝/外殼:40-VFQFN 裸露焊盤 包裝:帶卷 (TR) |
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