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參數(shù)資料
| 型號： | ISL6298CR4Z |
| 廠商： | INTERSIL CORP |
| 元件分類： | 電源管理 |
| 英文描述： | Quadruple 2-Input Exclusive-OR Gates 14-SSOP -40 to 85 |
| 中文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PQCC16 |
| 封裝： | 4 X 4 MM, LEAD FREE, PLASTIC, MO-220-VGGC, QFN-16 |
| 文件頁數(shù)： | 14/17頁 |
| 文件大?。?/td> | 445K |
| 代理商： | ISL6298CR4Z |
14
FN9173.3
July 20, 2005
The N-channel MOSFET Q
1
buffers the FAULT pin. The
gate of Q
1
is connected to VIN or the V2P8 pin. When the
FAULT pin outputs a logic low signal, Q
1
is turned on and its
drain outputs a low signal as well. When FAULT is high
impedance, R
1
pulls the Q
1
drain to high. When the input
power is removed, the Q
1
gate voltage is also removed, thus
the Q
1
drain stays high.
NTC Thermistor Circuit Design
As shown in Figure 21, the thresholds for the NTC circuit are
formed by the internal voltage divider. Since the external
circuit is also a voltage divider, the accuracy of the bias
voltage, that is, the V2P8 pin voltage, becomes not critical.
Figure 25 shows the typical values of the thresholds as
percentages of the V2P8 pin voltage.
The NTC thermistor resistance is dependent on the ambient
temperature. Reducing temperature leads to the increase of
the resistance as well as the TEMP pin voltage. When the
TEMP pin voltage exceeds 50.3% of the bias voltage, an
under-temperature fault is triggered. On the other hand, if
the TEMP pin voltage is lower than 12.5%, an over
temperature fault occurs. The TEMP pin voltage has to fall
back to the 14.5% to 42.9% range for the fault be cleared, as
shown in Figure 25.
The ratio, K, of the TEMP pin voltage to the bias voltage is:
(EQ. 6)
Using the ratios at cold and hot temperature limits, as shown
in Figure 25, resulting in:
(EQ. 7)
and
(EQ. 8)
where R
COLD
and R
HOT
are the NTC thermistor resistance
values at the cold and hot temperature limits respectively.
It is usually difficult to find an NTC thermistor that has the
exact ratio given in EQ. 7. A thermistor with a ratio larger
than 7.08, that is:
(EQ. 9)
can be used in series with a regular resistor to form an
effective thermistor that has the right ratio, as shown in
Figure 26. With the series resistor R
S
, EQ. 7 can be re-
written as:
(EQ. 10)
Once the thermistor and the temperature limits are selected,
R
S
and R
U
can be calculated using
(EQ. 11)
and
(EQ. 12)
To summarize, the NTC thermistor circuit design requires
three steps:
1. Find an NTC thermistor that satisfies EQ. 9. The
temperature limits are determined by the application
requirement.
2. Calculate the series resistance according to EQ. 11.
3. Calculate the pull-up resistance according to EQ. 12.
The following is a design example. The charger is designed
to charge the battery with the temperature range from 0°C to
55°C. The 10k
NTC thermistor NCP15XH103F03RC from
Murata (http://www.murata.com) satisfies EQ. 9. The
resistance table is given in Table 3. The typical resistance at
FIGURE 25. CRITICAL VOLTAGE LEVELS FOR TEMP PIN
100%
V
TMIN
(50.3%)
0
Under
Temp
Over
Temp
TEMP
Pin
Voltage
V
TMIN-
(42.9%)
V
TMAX
(12.5%)
V
TMAX+
(14.5%)
K
R
T
R
U
--------+
=
R
R
HOT
-------------------
7.08
=
R
U
1.012 R
COLD
=
R
HOT
-------------------
7.08
≥
FIGURE 26. EFFECTIVE NTC THERMISTOR CIRCUIT
ISL6298
V2P8
TEMP
GND
R
U
R
T
R
S
E
T
R
R
S
COLD
R
HOT
+
--------+
7.08
=
R
S
R
------------------------------------------------------
7.08R
–
=
R
U
1.012
R
S
R
COLD
+
(
)
=
ISL6298
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| ISL6298EVAL1 | 功能描述:EVALUATION BOARD 1 ISL6298 RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標準包裝:1 系列:PCI Express® (PCIe) 主要目的:接口，收發(fā)器，PCI Express 嵌入式:- 已用 IC / 零件:DS80PCI800 主要屬性:- 次要屬性:- 已供物品:板 |
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