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參數(shù)資料
| 型號： | ISL6140CB-T |
| 廠商： | INTERSIL CORP |
| 元件分類： | 電源管理 |
| 英文描述： | Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs 20-TSSOP -40 to 85 |
| 中文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO8 |
| 封裝： | MS-012-AA, PLASTIC, SOIC-8 |
| 文件頁數(shù)： | 11/18頁 |
| 文件大小： | 511K |
| 代理商： | ISL6140CB-T |
11
ISL6150 (H version) output that the given current will create
a high enough input voltage (remember that current through
the RPG 6.2k
resistor generates the high voltage level; see
Figure 9).
The input capacitance of the brick is chosen to match its
system requirements, such as filtering noise, and
maintaining regulation under varying loads. Note that this
input capacitance appears as the load capacitance of the
ISL6140/ISL6150.
The brick’s output capacitance is also determined by the
system, including load regulation considerations. However, it
can affect the ISL6140/ISL6150, depending upon how it is
enabled. For example, if the PWRGD signal is not used to
enable the brick, the following could occur. Sometime during
the inrush current time, as the main power supply starts
charging the brick input capacitors, the brick itself will start
working, and start charging its output capacitors and load;
that current has to be added to the inrush current. In some
cases, the sum could exceed the Over-Current shutdown,
which would shut down the whole system! Therefore,
whenever practical, it is advantageous to use the PWRGD
output to keep the brick off at least until the input caps are
charged up, and then start-up the brick to charge its output
caps.
Typical brick regulators include models such as Lucent
JW050A1-E or Vicor VI-J30-CY. These are nominal -48V
input, and 5V outputs, with some isolation between the input
and output.
Applications: Layout Considerations
For the minimum application, there are only 6 resistors, 2
capacitors, one IC and one FET. A sample layout is shown in
Figure 30. It assumes the IC is 8-SOIC; the FET is in a
D2PAK (or similar SMD-220 package).
Although GND planes are common with multi-level PCBs, for
a -48V system, the -48V rails (both input and output) act
more like a GND than the top 0V rail (mainly because the IC
signals are mostly referenced to the lower rail). So if
separate planes for each voltage are not an option, consider
prioritizing the bottom rails first.
Note that with the placement shown, most of the signal lines
are short, and there should not be much interaction between
them.
Although decoupling capacitors across the IC supply pins
are often recommended in general, this application may not
need one, nor even tolerate one. For one thing, a decoupling
cap would add to (or be swamped out by) any other input
capacitance; it also needs to be charged up when power is
applied. But more importantly, there are no high speed (or
any) input signals to the IC that need to be conditioned. If still
desired, consider the isolation resistor R10, as shown in
Figure 29.
ISL6140, ISL6150
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|---|---|
| ISL6140CBZ | Negative Voltage Hot Plug Controller |
| ISL6140IB | Negative Voltage Hot Plug Controller |
| ISL6150 | Octal D-Type Transparent Latches With 3-State Outputs 20-SSOP -40 to 85 |
| ISL6150CB | Octal D-Type Transparent Latches With 3-State Outputs 20-SSOP -40 to 85 |
| ISL6150CB-T | Octal D-Type Transparent Latches With 3-State Outputs 20-SSOP -40 to 85 |
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