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參數(shù)資料
| 型號(hào)： | ISL6130IRZA |
| 廠商： | INTERSIL CORP |
| 元件分類： | 電源管理 |
| 英文描述： | Power Sequencing Controllers |
| 中文描述： | 4-CHANNEL POWER SUPPLY SUPPORT CKT, PQCC24 |
| 封裝： | 4 X 4 MM, ROHS COMPLIANT, PLASTIC, QFN-24 |
| 文件頁(yè)數(shù)： | 17/21頁(yè) |
| 文件大?。?/td> | 488K |
| 代理商： | ISL6130IRZA |
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17
FN9005.8
February 5, 2007
If the mere presence of some voltage potential is adequate
prior to sequencing on, then a small number of standard
logic AND gates can be used to accomplish this. The block
diagram in Figure 18 illustrates this voltage presence
configuration.
In either case, the sequencing is straight forward across
multiple sequencers as all DLY_ON capacitors will
simultaneously start charging ~10ms after the common
ENABLE input signal is delivered. This allows the choice of
capacitors to be related to each other no different than using
a single sequencer. When the common enabling signal is
deasserted these configurations will then execute the
turn-off sequence across all sequencers as programmed by
the DLY_OFF capacitor values.
In both cases, with all the SYSRST# pins bussed together,
once the on sequence is complete, simultaneous shutdown
upon any UVLO input failure is assured as SYSRST# output
will momentarily pull low turning off all GATE and LOGIC
outputs.
There may be applications that require or allow groups of
supplies being brought up in sequence and supplies within
each group to be sequenced. Figure 19 illustrates such a
configuration that allows the first group of supplies to turn-on
before the second group starts. This arrangement does not
necessarily preclude adding the assurance of all supplies
prior to turn-on sequencing as previously shown but it will
prevent the turn-on sequence from completing if there is one
unsatisfied UVLO input in a group. Using this configuration
involves waiting through the T
UVLOdel
and T
RSTdel
(total of
~160ms) for each sequencer IC in the chain for the final
RESET# to release. Once ENABLE on the first sequencer is
deasserted all the RESET# outputs will quickly pull low and
thus allow the sequenced turn-off of this configuration to
ripple through several banks as quickly as the user
programmed sequence as chosen by the DLY_OFF
capacitors allow. Once again with common bussed
SYSRTS# pins, simultaneous shut down of all GATEs and
LOGIC down upon an unsatisfied UVLO input is assured
once all FETs or LOGIC output are on. If a GATE drive
option IC is used to drive both FETs and logic signals then
care to ensure the charged pump GATE does not over drive
and damage the logic input must be taken. A simple resistor
divider can be used to lower the GATE voltage to a suitable
voltage for the logic input as shown in Figure 19.
FIGURE 17. ISL612X AND ISL613X VOLTAGE COMPLIANT
SEQUENCING BLOCK DIAGRAM
ISL6125
# N+1
ENABLE#
ISL6124
# N
UVLO
ENABLE#
ISL613Xs
MONITORING
ON ALL RAILS
PGOOD
UVLO
VMON
G
A
T
E
L
O
G
I
C
POWER
SUPPLY
SYSRST#
SYSRST#
en
RESET#
RESET#
RESET#
OE
LOW = RESET
FIGURE 18. MULTIPLE ISL612X USING LOGIC GATES FOR
VOLTAGE PRESENCE DETECT
ISL6125
# N+1
ENABLE#
ISL6124
# N
UVLO
ENABLE#
UVLO
G
A
T
E
L
O
G
I
C
POWER
SUPPLY
SYSRST#
SYSRST#
en
RESET#’
RESET#
RESET#
UVLO
OE
LOW = RESET
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISL6130IRZA-T | 功能描述:IC POWER SUPPLY SEQUENCER 24QFN RoHS:是 類別:集成電路 (IC) >> PMIC - 電源控制器，監(jiān)視器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 應(yīng)用:多相控制器 輸入電壓:- 電源電壓:9 V ~ 14 V 電流 - 電源:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:40-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:40-TQFN-EP（5x5） 包裝:帶卷 (TR) |
| ISL6130IRZA-TS2378 | 制造商:Intersil Corporation 功能描述: |
| ISL6131 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Multiple Voltage Supervisory ICs |
| ISL6131EVAL1Z | 制造商:Intersil Corporation 功能描述:ISL6131 EVAL BOARD - 24 LEAD - MLFP - ROHS - Bulk 制造商:Intersil Corporation 功能描述:BOARD EVAL FOR ISL6131 |
| ISL6131IR | 功能描述:IC SUPERVISOR VOLT 4-LINE 24-QFN RoHS:否 類別:集成電路 (IC) >> PMIC - 監(jiān)控器 系列:- 標(biāo)準(zhǔn)包裝:100 系列:- 類型:簡(jiǎn)單復(fù)位/加電復(fù)位 監(jiān)視電壓數(shù)目:1 輸出:- 復(fù)位:低有效 復(fù)位超時(shí):最小為 100 ms 電壓 - 閥值:4.38V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:8-TSSOP 包裝:管件 |
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