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參數(shù)資料
| 型號： | ISL6127 |
| 廠商： | Intersil Corporation |
| 英文描述： | Power Sequencing Controllers |
| 中文描述： | 電源順序控制器 |
| 文件頁數(shù)： | 5/16頁 |
| 文件大?。?/td> | 422K |
| 代理商： | ISL6127 |
5
ISL6123, ISL6124, ISL6125 Descriptions
and Operation
The
ISL6123, ISL6124, ISL6125
sequencer family consists
of several four channel voltage sequencing controllers in
various functional and personality configurations. All are
designed for use in multiple-voltage systems requiring
power sequencing of various supply voltages. Individual
voltage rails are gated on and off by external N-Channel
MOSFETs, the gates of which are driven by an internal
charge pump to V
DD
+5.3V (VQP) in a user programmed
sequence.
With the four-channel
ISL6123
the ENABLE must be
asserted and all four voltages to be sequenced must be
above their respective user programmed Under Voltage
Lock Out (UVLO) levels before programmed output turn on
sequencing can begin. Sequencing and delay
determination is accomplished by the choice of external
cap values on the DLY_ON and DLY_OFF pins. Once all 4
UVLO inputs and ENABLE are satisfied for 10ms, the four
DLY_ON caps are simultaneously charged with 1
μ
A
current sources to the DLY_Vth level of 1.27V. As each
DLY_ON pin reaches the DLY_Vth level its associated
GATE will then turn-on with a 1
μ
A source current to the
VQP voltage of V
DD
+5.3V. Thus all four GATEs will
sequentially turn on. Once at DLY_Vth the DLY_ON pins
will discharge to be ready when next needed. After the
entire turn on sequence has been completed and all
GATEs have reached the charge pumped voltage (VQP), a
160ms delay is started to ensure stability after which the
RESET# output will be released to go high. Subsequent to
turn-on, if any input falls below its UVLO point for longer
than the glitch filter period (~30
μ
s) this is considered a
fault. RESET# and SYSRST# are pulled low and all GATEs
are simultaneously also pulled low. In this mode the GATEs
are pulled low with 88mA. Normal shutdown mode is
entered when no UVLO is violated and the ENABLE is
deasserted. When ENABLE is deasserted, RESET# is
asserted and pulled low. Next, all four shutdown ramp caps
on the DLY_OFF pins are charged with a 1
μ
A source and
when any ramp-cap reaches DLY_Vth, a latch is set and a
current is sunk on the respective GATE pin to turn off its
external MOSFET. When the GATE voltage is
approximately 0.6V, the GATE is pulled down the rest of
the way at a higher current level. Each individual external
FET is thus turned off removing the voltages from the load
in the programmed sequence.
The
ISL6123
and
ISL6124
have the same functionality
except for the ENABLE active polarity with the
ISL6124
having an ENABLE# input. Additionally the
ISL6123
also
has an ultra low power sleep state when ENABLE is low.
The
ISL6125
has the same personality as the
ISL6124
but
instead of charged pump driven GATE outputs it has open
drain LOGIC outputs that can be pulled up to a maximum of
V
DD
.
The
ISL6126
is unique in that it’s sequence on is not time
determined but voltage determined. It’s personality is that each
of the four channels operates independently so that once the IC
is biased and any one of the UVLO inputs is greater than the
0.63V internal reference, and ENABLE# input is also satisfied
the GATE for the associated UVLO input will turn-on. In turn the
other UVLO inputs need to be satisfied for the associated
GATEs to turn-on. 150ms after all GATEs are fully on (GATE
voltage = VQP) the RESET# is released to go high. The UVLO
inputs can be driven by either a previously turned on output rail
offering a voltage determined sequence or by logic signal
inputs. Any subsequent UVLO level < its programmed level will
pull the RESET# output low (if previously released), but will not
latch-off the other outputs. Predetermined turn-off is
accomplished by signaling ENABLE# high, this will cause
RESET# to latch low and all four GATE outputs to follow the
programmed turn off sequence similar to a ISL6124.
The
ISL6127
is a four channel sequencer pre-programmed for
A-B-C-D turn-on and D-C-B-A turn-off. After all four UVLO and
ENABLE# inputs are satisfied for ~10ms, the sequencing starts
and the next GATE in the sequence starts to ramp up once the
previous GATE has reached ~VQP-1V. 160ms after the last
GATE is at VQP the RESET# output will be deasserted. Once
any UVLO is unsatisfied, RESET# is pulled low, SYSRST# is
pulled low and all GATEs are simultaneously turned off. When
ENABLE# is signaled high the D GATE will start to pull low and
once below 0.6V the next GATE will then start to pull low and
so on until all GATEs are at 0V. Unloaded, this turn off
sequence will complete in <1ms. This variant offers a lower
GATE High Voltage
V
GATEh
V
GATE_
Gate High Voltage
V
DD
+5V
-
V
DD
+5.3V
0
-
V
GATE Low Voltage
Gate Low Voltage, V
DD
= 1V
0.1
V
BIAS
IC Supply Current
I
VDD_5V
I
VDD_3.3V
I
VDD_1.5V
I
VDD_sb
V
DD
_POR
V
DD
= 5V
V
DD
= 3.3V
V
DD
= 1.5V
V
DD
= 5V, ENABLE = 0V
-
0.20
0.5
mA
IC Supply Current
-
0.14
-
mA
IC Supply Current
-
0.10
-
mA
ISL6123 Stand By IC Supply Current
-
-
1
μ
A
V
DD
Power On Reset
-
-
1
V
Electrical Specifications
V
DD
= 1.5V to +5V, T
A
= T
J
= -40
o
C - 85
o
C, Unless Otherwise Specified.
(Continued)
SYMBOL
TEST CONDITIONS
PARAMETER
MIN
TYP
MAX
UNIT
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128
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參數(shù)描述 |
|---|---|
| ISL6127IR | 功能描述:IC SEQUENCER POWER 4-CH 24-QFN RoHS:否 類別:集成電路 (IC) >> PMIC - 電源控制器，監(jiān)視器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 應(yīng)用:多相控制器 輸入電壓:- 電源電壓:9 V ~ 14 V 電流 - 電源:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:40-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:40-TQFN-EP（5x5） 包裝:帶卷 (TR) |
| ISL6127IR-T | 功能描述:IC CTRLR PWR SEQUENCE 4CH 24-QFN RoHS:否 類別:集成電路 (IC) >> PMIC - 電源控制器，監(jiān)視器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 應(yīng)用:多相控制器 輸入電壓:- 電源電壓:9 V ~ 14 V 電流 - 電源:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:40-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:40-TQFN-EP（5x5） 包裝:帶卷 (TR) |
| ISL6127IRZA | 功能描述:IC POWER SUPPLY SEQUENCER 24QFN RoHS:是 類別:集成電路 (IC) >> PMIC - 電源控制器，監(jiān)視器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 應(yīng)用:多相控制器 輸入電壓:- 電源電壓:9 V ~ 14 V 電流 - 電源:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:40-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:40-TQFN-EP（5x5） 包裝:帶卷 (TR) |
| ISL6127IRZA-T | 功能描述:IC POWER SUPPLY SEQUENCER 24QFN RoHS:是 類別:集成電路 (IC) >> PMIC - 電源控制器，監(jiān)視器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 應(yīng)用:多相控制器 輸入電壓:- 電源電壓:9 V ~ 14 V 電流 - 電源:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:40-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:40-TQFN-EP（5x5） 包裝:帶卷 (TR) |
| ISL6128 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Power Sequencing Controllers |
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