參數(shù)資料
型號： ISL6124
廠商： Intersil Corporation
英文描述： Power Sequencing Controllers
中文描述： 電源順序控制器
文件頁數(shù)： 4/16頁
文件大小： 422K
代理商： ISL6124
4
Absolute Maximum Ratings
Thermal Information
V
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.0V
GATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to V
DD
+6V
ISL6125 LOGIC OUT. . . . . . . . . . . . . . . . . . . . . -0.3V to V
DD
+0.3V
UVLO, ENABLE, ENABLE#, SYSRST# . . . . . . -0.3V to V
DD
+0.3V
RESET#, DLY_ON, DLYOFF . . . . . . . . . . . . . . -0.3V to V
DD
+0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0kV (HBM)
Operating Conditions
V
DD
Supply Voltage Range. . . . . . . . . . . . . . . . . . . .+1.5V to +5.5V
Temperature Range (T
A
). . . . . . . . . . . . . . . . . . . . . . -40
o
C to 85
o
C
Thermal Resistance (Typical, Notes 1, 2)
4 x 4 QFN Package . . . . . . . . . . . . . . .
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . .150
o
C
Maximum Storage Temperature Range . . . . . . . . . -65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300
o
C
(QFN - Leads Only)
θ
JA
(
o
C/W)
48
θ
JC
(
o
C/W)
9
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1.
θ
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2. For
θ
JC
, the “case temp” location is the center of the exposed metal pad on the package underside.
3. All voltages are relative to GND, unless otherwise specified.
Electrical Specifications
V
DD
= 1.5V to +5V, T
A
= T
J
= -40
o
C - 85
o
C, Unless Otherwise Specified.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
UVLO
Undervoltage Lockout Threshold
V
UVLOvth
TC
UVLOvth
V
UVLOhys
RUVLOvth
T
J
= +25
o
C
T
J
= -40
o
C to 85
o
C
619
633
647
mV
nV/
o
C
Undervoltage Lockout Threshold Temp Co
-
40
-
Undervoltage Lockout Hysteresis
-
10
-
mV
Undervoltage Lockout Threshold Range
Max V
UVLOvth
- Min V
UVLOvth
ENABLE satisfied
-
7
-
mV
Undervoltage Lockout Delay
TUVLOdel
-
10
-
ms
Transient Filter Duration
TFIL
V
DD
, UVLO, ENABLE glitch filter
-
30
-
μ
s
DELAY ON/OFF
Delay Charging Current
DLY_ichg
V
DLY
= 0V
DLY_ichg(max) - DLY_ichg(min)
0.92
1
1.08
μ
A
Delay Charging Current Range
DLY_ichg_r
-
0.08
-
μ
A
Delay Charging Current Temp. Coeff.
TC_DLY_ichg
-
0.2
-
nA/
o
C
Delay Threshold Voltage
DLY_Vth
1.238
1.266
1.294
V
Delay Threshold Voltage Temp. Coeff.
TC_DLY_Vth
-
0.2
-
mV/
o
C
ENABLE/ENABLE#, RESET# & SYSRST# I/O
ENABLE Threshold
V
ENh
V
ENh
-
1.2
-
V
ENABLE# Threshold
-
V
DD
/2
0.2
-
V
ENABLE/ENABLE# Hysteresis
V
ENh -
V
ENl
TdelEN_LO
Measured at V
DD
= 1.5V
UVLO satisfied
-
-
V
ENABLE/ENABLE# Lockout Delay
-
10
-
ms
RESET# Pull-Down Current
I
RSTpd
T
RSTdel
V
RSTl
RST = 0.1V
-
13
-
mA
RESET# Delay after GATE High
GATE = V
DD
+5V
Measured at V
DD
= 5V with 5K
pullup resistors
-
160
-
ms
RESET# Output Low
-
-
0.001
V
SYSRST# Low to GATE Turn-off
T
delSYS_G
GATE = 80% of V
DD
+5V
-
40
-
ns
GATE
GATE Turn-On Current
I
GATEon
I
GATEoff_l
I
GATE_range
TC_I
GATE
I
GATEoff_h
GATE = 0V
0.8
1.1
1.4
μ
A
GATE Turn-Off Current
GATE = V
DD
, Disabled
Within IC I
GATE
max-min
-1.4
-1.05
-0.8
μ
A
GATE Current Range
-
-
0.35
μ
A
GATE Turn-On/Off Current Temp. Coeff.
-
0.2
-
nA/
o
C
GATE Pull-Down High Current
GATE = V
DD
, UVLO = 0V
-
88
-
mA
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