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參數(shù)資料
| 型號(hào)： | ISL59923IRZ-T7 |
| 廠商： | Intersil |
| 文件頁(yè)數(shù)： | 6/16頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC ANLG VID LINE TRPL 20-QFN |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | 視頻延遲線 |
| 應(yīng)用： | RGB 視頻信號(hào) |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-VQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 20-QFN 裸露焊盤（5x5） |
| 包裝： | 帶卷 (TR) |
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14
FN6826.2
August 31, 2010
These steps are only necessary if the sync signal is
embedded on the video and you want to avoid possible
monitor blanking during skew adjustment.
Test Pins
Three test pins are provided (Test R, Test G, Test B). During
normal operation, the test pins output pulses of current for a
duration of the overlap between the inputs, as shown in
Figure 34:
TESTR pulse = REDOUT (A) with respect to GREENOUT (B)
TESTG pulse = GREENOUT with respect to BLUEOUT
TESTB pulse = BLUEOUT with respect to REDOUT
Averaging the current gives a direct measure of the delay
between the two edges. When A precedes B, the current
pulse is +50A, and the output voltage goes up. When B
precedes A, the pulse is -50A.
For the logic to work correctly, A and B must have a period of
overlap while they are high (a delay longer than the pulse
width cannot be measured).
Signals A and B are derived from the video input by
comparing the video signal with a slicing level, which is set by
an internal DAC. This enables the delay to be measured
either from the rising edges of sync-like signals encoded on
top of the video or from a dedicated set-up signal. The outputs
can be used to set the correct delays for the signals received.
The DAC level is set through the serial input by bits 1
through 4 directed to the test register (00).
Internal DAC Voltage
The slice level of the internal DAC may be programmed by
writing a byte to the test register (00). Table 3 shows the
values that should be written to change the DAC slice level.
Please keep in mind when writing to the test register that the
LSB should always be zero.
Referred to the input, the DAC slice range for the ISL5992x
is cut in half for gain of 2 mode because the slicing occurs
after the x1/x2 stage output amplifier. (In the EL9115, the
slicing occurred before the amplifier so the range of the DAC
voltage was the same for either gain of 1 or gain of 2).
TABLE 3. DAC VOLTAGE RANGE - INPUT REFERRED
wxyz
DAC RANGE [mV]
(GAIN 1)
DAC RANGE [mV]
(GAIN 2)
1000
-400
-200
1001
-350
-175
1010
-300
-150
1011
-250
-125
1100
-200
-100
1101
-150
-75
1110
-100
-50
1111
-50
-25
0000
0
0001
50
25
0010
100
50
0011
150
75
0100
200
100
0101
250
125
0110
300
150
0111
350
175
NOTE: Test Register word = 000wxyz0. wxyz fed to DAC. z is LSB
FIGURE 34. DELAY DETECTOR
A
B
OUTPUT
4
SLICING LEVEL
COMPARATORS
A
B
INTERNAL DAC
000wxyz0
TESTR
A
B
TESTG
A
B
TESTB
REDOUT
GREENOUT
BLUEOUT
ISL59920, ISL59921, ISL59922, ISL59923
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