14 FN7548.0 September 2, 2011 Configuration Register Write Figure 17 shows two views of the steps necessary to write one or more words" />
參數(shù)資料
型號: ISL59911IRZ-EVALZ
廠商: Intersil
文件頁數(shù): 6/17頁
文件大?。?/td> 0K
描述: EVALUATION BOARD FOR ISL59911
標(biāo)準(zhǔn)包裝: 1
ISL59911
14
FN7548.0
September 2, 2011
Configuration Register Write
Figure 17 shows two views of the steps necessary to write one or
more words to the Configuration Register.
SCL
SDA
DATA STABLE
DATA CHANGE
DATA STABLE
FIGURE 16. VALID DATA CHANGES ON THE SDA BUS
D7
D6
D5
D2
D4
D3
D1
D0
A0
A7
A2
A4
A3
A1
ISL59911 Register Data Write(s)
This is the data to be written to the ISL59911’s Configuration
Register. Note: The ISL59911 Configuration Register’s address
pointer auto-increments after each data write. Repeat this step to
write multiple sequential bytes of data to the Configuration Register.
A6
A5
0
R/W
ISL59911 Register Address Write
This is the address of the ISL59911’s Configuration Register
that the following byte will be written to.
ISL59911 Serial Bus
FIGURE 17. CONFIGURATION REGISTER WRITE
START Command
STOP Command
(Repeat if desired)
Signals the beginning of serial I/O
Signals the ending of serial I/O
S
T
A
R
T
S
T
O
P
Data
Write*
Register
Address
Serial Bus
Address
A
C
K
AAAAAAAA
A
C
K
dddddddd
A
C
K
aaaaaaa0
* The Data Write step can be repeated to write to the
ISL59911’s Configuration Register sequentially, beginning at
the Register Address written in the previous step.
SDA Bus
Signals from
the ISL59911
Signals from
the Host
ISL59911 Device Select Address Write
The first 7 bits of the first byte select the ISL59911 on the 2-wire
bus at the address set by the ADDR0 and ADDR1 pins. The
R/W bit is a 0, indicating that the next transaction will be a write.
ADDR1 ADDR0
01
00
1
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