![](http://datasheet.mmic.net.cn/Intersil/ISL59885IS-T7_datasheet_105301/ISL59885IS-T7_4.png)
ISL59885
4
FN7442.8
October 31, 2011
Typical Performance Curves
FIGURE 2. HSYNC vs VCSET (RSET = OPEN)
FIGURE 3. HSYNC PULSE WIDTH vs HSYNC FREQUENCY
(RSET = OPEN)
FIGURE 4. HSYNC vs VCSET (RSET = OPEN)
FIGURE 5. MACROVISION COMPATIBILITY (NTSC)
FIGURE 6. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
HSYNC (Hz)
V
CSET
(V)
VDD = 3.3 AND 5.0V
k
kk
k
kk
k
HSYNC FREQUENCY (Hz)
H
SY
N
C
PULSE
WIDTH
(ns)
VDD = 3.3 AND 5.0V
kk
k
VCSET (V)
H
SY
N
C
BLANK
ING
TIME
(
s)
VDD = 3.3 AND 5.0V
0.5V/DIV
5V/DIV
HSYNC
VSYNC
CSYNC
VIN
100s/DIV
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
0
0.2
0.4
0.6
0.8
1.0
1.2
0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90
AMBIENT TEMPERATURE (°C)
8 PIN SOIC PACKAGE
θJA= 120°C/W
MAX
P
O
WE
R
DI
SSI
P
A
TI
ON
(W)