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參數(shù)資料
| 型號(hào)： | ISL5957EVAL1 |
| 廠商： | Intersil Corporation |
| 英文描述： | 14-Bit, +3.3V, 260+MSPS, High Speed D/A Converter |
| 中文描述： | 14位，3.3伏，260 MSPS的，高速D / A轉(zhuǎn)換 |
| 文件頁(yè)數(shù)： | 3/13頁(yè) |
| 文件大?。?/td> | 630K |
| 代理商： | ISL5957EVAL1 |
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3
FN6080.1
November 12, 2004
Pin Descriptions
PIN NO.
PIN NAME
DESCRIPTION
1-14
D13 (MSB) Through
D0 (LSB)
Digital Data Bit 13, (Most Significant Bit) through Digital Data Bit 0, (Least Significant Bit).
15
SLEEP
Control Pin for Power-Down mode. Sleep Mode is active high; Connect to ground for Normal Mode. Sleep
pin has internal 20
μ
A active pulldown current.
16
REFLO
Connect to analog ground to enable internal 1.2V reference or connect to AV
DD
to disable internal
reference.
17
REFIO
Reference voltage input if internal reference is disabled. Reference voltage output if internal reference is
enabled. Use 0.
1μ
F cap to ground when internal reference is enabled.
18
FSADJ
Full Scale Current Adjust. Use a resistor to ground to adjust full scale output current. Full Scale Output
Current = 32 x V
FSADJ
/R
SET
.
19, 25
NC
No Connect. These should be grounded, but can be left disconnected.
21
IOUTB
The complementary current output of the device. Full scale output current is achieved when all input bits
are set to binary 0.
22
IOUTA
Current output of the device. Full scale output current is achieved when all input bits are set to binary 1.
23
COMP
Connect 0.1
μ
F capacitor to ACOM.
24
AV
DD
Analog Supply (+2.7V to +3.6V).
20
ACOM
Connect to Analog Ground.
26
DCOM
Connect to Digital Ground.
27
DV
DD
Digital Supply (+2.7V to +3.6V).
28
CLK
Clock Input.
ISL5957
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