FN6220.8 April 13, 2011 Serial Timing Diagram Programming Model The ISL59530 is configured by a series of 16-bit serial control w" />
參數(shù)資料
型號(hào)： ISL59530IRZ
廠商： Intersil
文件頁(yè)數(shù)： 13/26頁(yè)
文件大?。?/td> 0K
描述： IC VIDEO CROSSPOINT SWITCH 72QFN
標(biāo)準(zhǔn)包裝： 168
功能： 視頻交叉點(diǎn)開(kāi)關(guān)
電路： 1 x 16:16
電流 - 電源： 320mA
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 72-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 72-QFN（10x10）
包裝： 托盤
20
FN6220.8
April 13, 2011
Serial Timing Diagram
Programming Model
The ISL59530 is configured by a series of 16-bit serial control words. The three MSBs (B15 through B13) of each serial word
determine the basic command:
Mapping Inputs to Outputs
Inputs are mapped to their desired outputs using the input/output control word. Its format is:
I3:I0 form the 4-bit word indicating the input channel (0 to 15), and O3:O0 determine the output channel which that input channel
will map to. One input can be mapped to one or multiple outputs. To fully program the ISL59530, 16 INPUT/OUTPUT words must
be transmitted - one for each input channel.
Note: Broadcast Mode must be disabled when configuring input/output mapping. INPUT/OUTPUT words transmitted while in
Broadcast Mode will not be processed correctly and result in corrupt channel mapping when Broadcast Mode is disabled.
TABLE 1. SERIAL TIMING PARAMETERS
PARAMETER
RECOMMENDED OPERATING RANGE
DESCRIPTION
t
≥200ns
SCLK period
tW
0.50*t
Clock Pulse Width
tSD
≥20ns
Data Setup Time
tHD
≥20ns
Data Hold Time
tSL
≥20ns
Final SLCK rising edge (latching B15) to SLATCH rising edge
TABLE 2. COMMAND FORMAT
B15
B14
B13
COMMAND
NUMBER OF WRITES
0
INPUT/OUTPUT: Maps input channels to output channels
16 (1 channel per write)
0
1
OUTPUT ENABLE: Output enable for individual channels
4 (4 channels per write)
0
1
0
GAIN SET: Gain (x1 or x2) for each channel
4 (4 channels per write)
0
1
BROADCAST: Enables broadcast mode and selects the input channel to be
broadcast to all output channels
1
CONTROL: Clamp on/off, operational/standby mode, and global output
enable/disable
1
TABLE 3. INPUT/OUTPUT WORD
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
00
0
I3
I2
I1
I0
00
O3
O2
O1
O0
0
SLATCH falling edge timing/placement is a “don’t care.”
Serial data is latched only on rising edge of SLATCH.
SLATCH
SCLK
tw
tSL
tSD
tHD
t
SDI
B0
(LSB)
B1
B2
B15
(MSB)
B0
(LSB)
B1
B2
B15
(PREVIOUS)
SDO
B0
(PREVIOUS)
B1
)(PREVIOUS)
B2
(PREVIOUS)
SDO = SDI delayed by 15.5 SCLKs to allow daisy-chaining of multiple ISL59530s. SDO changes on the falling edge of SCLK.
ISL59530
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