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參數(shù)資料
| 型號： | ISL58328CIZ-T7 |
| 廠商： | Intersil |
| 文件頁數(shù)： | 4/14頁 |
| 文件大?。?/td> | 380K |
| 描述： | IC LASER PWR MONITOR 5V 9CSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 傳感器類型： | 光學(xué) |
| 輸出類型： | 電壓 |
| 其它名稱： | ISL58328CIZ-T7DKR ISL58328CIZ-T7TRDKR ISL58328CIZ-T7TRDKR-ND |
ISL58328
4
FN6329.2
July 29, 2013
Absolute Maximum Ratings
Thermal Information
Supply Voltage (+5.0V to GND). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6.0V
Maximum CMOS Input/Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3.6V
Maximum Output Voltage . . . . . . . . . . . . . . . . . . . . . . V
SS
- 0.3 to V
DD
+ 0.3
ESD Rating
Human Body Model (Per MIL-STD-883 Method 3015.7). . . . . . . . . . 2kV
Machine Model (Per EIAJ ED-4701 Method C-111) . . . . . . . . . . . . . 200V
Latch Up (Tested per JESD-78) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mA
Thermal Resistance (Typical)
?/DIV>
JA
(?/SPAN>C/W) ?/SPAN>
JC
(?/SPAN>C/W)
9 Ld OCSP (Note 5). . . . . . . . . . . . . . . . . . . .
125
NA
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-25癈 to +125癈
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250癈
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty
NOTE:
5. ?/DIV>
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379
for details.
DC Electrical Specifications V
DD
= 5.0V, T
A
= +25癈 unless otherwise specified.
PARAMETER
DESCRIPTION
CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNIT
V
DD
+5.0V Supply Voltage Range
4.5
5.0
5.5
V
I
VDD1
Supply Current
No incident light, in nomal mode
20
25
mA
I
VDD2
Supply Current
No incident light, in SLEEP mode
600
礎(chǔ)
V
OFS
Output P Offset
Referenced to VREF
No incident light
-50
10
+50
mV
V
REF_i
Common Mode Output Voltage
Internal VREF generator
1.75
2.10
2.35
V
V
IL
CMOS Input LOW
SEN, SDATA, SCLK, and HL pins
0
0.8
V
VI
H
CMOS Input HIGH
SEN, SDATA, SCLK and HL pins
2.4
3.6
V
V
OL
CMOS Output LOW
SDATA; I
LOAD
= 3mA
0.8
V
V
OH
CMOS Output HIGH
SDATA; I
LOAD
= 3mA
2.5
V
NOTE:
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
AC Electrical Specifications V
DD
= 5.0V, T
A
= +25癈 unless otherwise specified.
PARAMETER
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
BW
Bandwidth
OUTP, OUTN (not differential)
-3dB
RBW = 30kHz
85
MHz
V
OUTMAX
Differential Mode Output Voltage
(OUTP) (OUTN)
Linear output
2.95
V
P-P
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