VDD = +3.6V, V
參數資料
型號: ISL54405IVZ
廠商: Intersil
文件頁數: 16/19頁
文件大?。?/td> 0K
描述: IC MUX STEREO 2:1 CD/MP3 16TSSOP
標準包裝: 96
功能: 開關
電路: 2 x SPDT
導通狀態(tài)電阻: 1.9 歐姆
電壓電源: 單電源
電壓 - 電源,單路/雙路(±): 3 V ~ 3.6 V
電流 - 電源: 55µA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-TSSOP(0.173",4.40mm 寬)
供應商設備封裝: 16-TSSOP
包裝: 管件
產品目錄頁面: 1247 (CN2011-ZH PDF)
6
FN6699.1
June 5, 2008
Positive Supply Current, I+
VDD = +3.6V, VMUTE = 0V, VSEL = 0V or VDD
3.6V
25
-
54
65
μA
Full
-
59
-
μA
VDD = +3.6V, VMUTE = VDD, VSEL = 0V or VDD
3.6V
25
-
14
18
μA
3.6V
Full
-
15
-
μA
VDD = +3.6V, VMUTE = 0V, VSEL = 1.8V
3.6V
25
-
55
65
μA
3.6V
Full
-
58
-
μA
DIGITAL INPUT CHARACTERISTICS
Input Voltage Low, VSELL,
VMUTEL
3.3V,
5V
Full
-
0.5
V
Input Voltage High, VSELH,
VMUTEH
3.3V,
5V
Full
1.4
-
V
Input Current, ISELH, ISELL VDD = 3.6V, VMUTE = 0V, VSEL = 0V or VDD
3.6V
Full
-0.5
0.01
0.5
A
Input Current, IAC/DCL,
IDIR_SELL
VDD = 3.6V, VAC/DC, VDIR_SEL = 0V,
VMUTE = Float, VSEL = VDD
3.6V
Full
-1.3
-0.7
0.3
A
Input Current, IAC/DCH,
IDIR_SELH
VDD = 3.6V, VAC/DC, VDIR_SEL = VDD,
VMUTE =0V, VSEL = 0V
3.6V
Full
-0.5
0.01
0.5
A
Input Current, IMUTEL
VDD = 3.6V, VSEL = VDD, VMUTE = 0V
3.6V
Full
-1.3
-0.7
0.3
A
Input Current, IMUTEH
VDD = 3.6V, VSEL = 0V, VMUTE = VDD
3.6V
Full
-0.5
0.01
0.5
A
NOTES:
8. VIN = input voltage to perform proper function.
9. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
10. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
11. Flatness is defined as the difference between maximum and minimum value of ON-resistance at the specified analog signal voltage points.
12. Limits established by characterization and are not production tested.
13. rON matching between channels is calculated by subtracting the channel with the highest max rON value from the channel with lowest max rON
value.
Test Circuits and Waveforms
Logic input waveform is inverted for switches that have the opposite
logic sense.
FIGURE 1A. MEASUREMENT POINTS
Repeat test for all switches. CL includes fixture and stray
capacitance.
FIGURE 1B. TEST CIRCUIT
Electrical Specifications - 3.3V Supply Test Conditions: V
DD = +3.0V to +3.6V, GND = 0V, VDIR_SEL = VAC/DC = GND,
V5V_SUPPLY = Float, VSIGNAL = 2VRMS, RLOAD = 20kΩ, f = 1kHz,
VSELH = VMUTEH = 1.4V, VSELL = VMUTEL = 0.5V, CAP_SS = 0.1F, (Note 8),
Unless Otherwise Specified. (Continued)
PARAMETER
TEST CONDITIONS
SUPPL
Y
TEM
P
(°C)
MIN
(Notes 9, 10)
TYP
MAX
(Notes 9, 10) UNITS
50%
tr < 20ns
tf < 20ns
tOFF
90%
VDD
0V
VLx OR VRx
0V
tON
LOGIC
INPUT
SWITCH
INPUT
SWITCH
OUTPUT
90%
VOUT
V
OUT
V
(Lx or Rx)
R
L
R
L
r
ON
+
------------------------
=
SWITCH
INPUT
LOGIC
INPUT
VOUT
RL
CL
L or R
Lx OR Rx
SEL
GND
VDD
C
MUTE
ISL54405
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