參數(shù)資料
型號(hào): ISL54302IRZ
廠商: Intersil
文件頁數(shù): 15/16頁
文件大?。?/td> 0K
描述: IC SWITCH QUAD SPST 20QFN
標(biāo)準(zhǔn)包裝: 75
功能: 開關(guān)
電路: 4 x SPST - NO
導(dǎo)通狀態(tài)電阻: 2 歐姆
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 20-QFN(4x4)
包裝: 管件
8
March 19, 2008
Supply Sequencing and Overvoltage Protection
With any CMOS device, proper power supply sequencing is
required to protect the device from excessive input currents,
which might permanently damage the IC. All switch contact
I/O pins contain ESD protection diodes from the pin to
VPLUS and to VSS (see Figure 7). To prevent forward
biasing these diodes, VPLUS, GND and VSS must be
applied before any input signals, and switch signal voltages
must remain between VPLUS and VSS. Digital control
signals should be limited to VLOGIC and VSS.
SPECIFIC POWER SEQUENCE
1. GND
2. VSS Typical . . . . . . . . . . . 3V to 0V with respect to GND
3. VPLUS Typical . . . . . . . +5V to +9V with respect to GND
4. VDD . . . . . . . . . . . . . . . . . . . +3V to with respect to VSS
5. VLOGIC . . . . . . . . . . . . . . . . . . +3V with respect to GND
If these conditions cannot be guaranteed, then one of the
following two protection methods should be employed.
Logic inputs can easily be protected by adding a 1k
Ω
resistor in series with the input. The resistor limits the input
current below the threshold that produces permanent
damage, and the sub-microamp input current produces an
insignificant voltage drop during normal operation.
Adding a series resistor to the switch input defeats the purpose
of using a low rON switch, so two small signal diodes can be
added in series with the supply pins to provide overvoltage
protection for all pins (see Figure 7). These additional diodes
limit the analog signal from 1V below VPLUS to 1V above VSS.
The leakage current performance is unaffected by this
approach, but the switch resistance may increase, especially
at low supply voltages.
ESD Protection
The device contains ESD protection on the device pins.
These devices are design to work based on dV/dt. During
power-up, the user should review the rise/fall times on the
power connections. The rise time of the power rails should
not be faster than 1s.
SW1-A
S2
-CTRL
S1
-CTRL
S1 CONTROL
S4
-CTRL
LEVEL
SHIFTER
S3
-CTRL
CS-LA
T
CH
SW1-B
SW2-A
S2 CONTROL
SW2-B
SW3-B
S3 CONTROL
SW3-A
SW4-B
S4 CONTROL
SW4-A
INTERNAL
CS-LATCH
REGISTERS
INTERNAL
CS-LATCH
REGISTERS
LEVEL
SHIFTER
LEVEL
SHIFTER
LEVEL
SHIFTER
LEVEL
SHIFTER
FIGURE 6. ISL54302 FUNCTIONAL DIAGRAM
FIGURE 7. ESD/OVERVOLTAGE PROTECTION
CLAMP
VPLUS
VSS
CLAMP
VDD
VSS
CLAMP
VLOGIC
GND
VPLUS
ONE FOR EACH PIN LISTED: 1A, 1B, 2A, 2B, 3A, 3B, 4A, 4B,
VLOGIC
GND
ONE FOR EACH PIN LISTED: S1-CTRL, S2-CTRL,
VSS
VDD, VLOGIC
S3-CTRL, S4-CTRL, CS-LATCH
ISL54302
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