參數(shù)資料
型號: ISL54050
廠商: Intersil Corporation
英文描述: Ultra Low ON-Resistance, +1.65V to +4.5V, Single Supply, Dual SPDT Analog Switch(超低導(dǎo)通電阻, +1.65V到+4.5V, 單電源, 雙路單刀雙擲模擬開關(guān))
中文描述: 超低電阻,從1.65V至4.5V,單電源,雙路SPDT模擬開關(guān)(超低導(dǎo)通電阻,從1.65V到4.5V時(shí),單電源,雙路單刀雙擲模擬開關(guān))
文件頁數(shù): 7/12頁
文件大?。?/td> 290K
代理商: ISL54050
7
FN6356.2
June 11, 2007
Detailed Description
The ISL54050 is a bidirectional, dual single pole/double
throw (SPDT) analog switch that offers precise switching
capability from a single 1.65V to 4.5V supply with low
ON-resistance (0.29
Ω
) and high speed operation
(t
ON
= 40ns, t
OFF
= 20ns). The device is especially well
suited for portable battery powered equipment due to its low
operating supply voltage (1.65V), low power consumption
(4.5
μ
W max), low leakage currents (195nA max), and the tiny
μ
TQFN package. The ultra low ON-resistance and r
ON
flatness provide very low insertion loss and distortion to
applications that require signal reproduction.
External V+ Series Resistor
For improved ESD and latch-up immunity, Intersil
recommends adding a 100
Ω
resistor in series with the V+
power supply pin of the ISL54050 IC (see Figure 8).
During an overvoltage transient event, such as occurs during
system level IEC 61000 ESD testing, substrate currents can
be generated in the IC that can trigger parasitic SCR
structures to turn ON, creating a low impedance path from
the V+ power supply to ground. This will result in a
significant amount of current flow in the IC, which can
potentially create a latch-up state or permanently damage
the IC. The external V+ resistor limits the current during this
over-stress situation and has been found to prevent latch-up
or destructive damage for many overvoltage transient
events.
Under normal operation the sub-microamp I
DD
current of the
IC produces an insignificant voltage drop across the 100
Ω
series resistor resulting in no impact to switch operation or
performance.
FIGURE 4. OFF ISOLATION TEST CIRCUIT
FIGURE 5. r
ON
TEST CIRCUIT
FIGURE 6. CROSSTALK TEST CIRCUIT
FIGURE 7. CAPACITANCE TEST CIRCUIT
Test Circuits and Waveforms
(Continued)
ANALYZER
R
L
SIGNAL
GENERATOR
V+
C
0V or V+
NO or NC
COM
IN
GND
Signal direction through switch is reversed, worst case values
are recorded. Repeat test for all switches.
V+
C
0V or V+
NO or NC
COM
IN
GND
V
NX
V
1
r
ON
= V
1
/100mA
100mA
Repeat test for all switches.
0V or V+
ANALYZER
V+
C
NO or NC
SIGNAL
GENERATOR
R
L
GND
IN
1
COM
50
Ω
N.C.
COM
NC or NO
Signal direction through switch is reversed, worst case values
are recorded. Repeat test for all switches.
V+
C
GND
NO or NC
COM
IN
IMPEDANCE
ANALYZER
0V or V+
Repeat test for all switches.
ISL54050
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