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參數(shù)資料
| 型號： | ISL5217KI |
| 廠商： | INTERSIL CORP |
| 元件分類： | 無繩電話/電話 |
| 英文描述： | Quad Programmable Up Converter |
| 中文描述： | TELECOM, CELLULAR, BASEBAND CIRCUIT, PBGA196 |
| 封裝： | 15 X 15 MM, PLASTIC, BGA-196 |
| 文件頁數(shù)： | 32/43頁 |
| 文件大?。?/td> | 766K |
| 代理商： | ISL5217KI |
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32
5
Sample Rate Divider
4
Sample Rate Freq
3
Sample Fine Phase
2
Sample Coarse Phase
1
Routing Control
0
I Strobe
1 = Update, 0 = No Update.
NOTES:
25. The mask register enables the slave registers to be updated from a hardware or software strobe.
26. The mask register is not used when
μ
P is updating a configuration slave register immediately.
27. There is no immediate update on the I strobe.
28. Update mask <1> only affects the top routing control nibble for this channel.
TABLE 30. UPDATE MASK (Continued)
TYPE: SINGLE CHANNEL DIRECT, ADDRESS: 0x0e
BIT
FUNCTION
DESCRIPTION
TABLE 31. IMMEDIATE ACTION
TYPE: SINGLE CHANNEL DIRECT, ADDRESS: 0x0f
BIT
FUNCTION
DESCRIPTION
15:2
Reserved
Not used
1
Soft Reset
(Channel Reset)
Soft reset. Self clearing pulse zeroes FIFO’s, zeroes data RAMs, and clears all but the master registers.
The device will reload the slave configuration registers on the next TX enable or update strobe
0
Software Update
(General Update)
Software update Self clearing pulse allows
μ
P write to load all configuration slave registers synchronously
as determined by the update mask. The software equivalent of the hardware Update strobe
TABLE 32. POLARITY CONTROL
TYPE: SINGLE CHANNEL DIRECT, ADDRESS: 0x10
BIT
FUNCTION
DESCRIPTION
15:4
Reserved
N/A
3
Tx Enable Polarity
TX enable polarity
0 = defines an assertion as a transition from a logic low to a logic high
1 = defines an assertion as a transition from a logic high to a logic low
2
Update Polarity
Update polarity.
0 = defines an assertion as a transition from a logic low to a logic high
1 = defines an assertion as a transition from a logic high to a logic low
1
FSR Polarity
Frame strobe polarity.
0 = defines an assertion as a transition from a logic low to a logic high
1 = defines an assertion as a transition from a logic high to a logic low
0
Serial CLK Polarity
Serial clk polarity.
0 = defines an assertion as a transition from a logic low to a logic high
1 = defines an assertion as a transition from a logic high to a logic low
0 =
1 =
0 =
1 =
0 =
1 =
0 =
1 =
ISL5217
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