參數資料
型號: ISL3332IAZ
廠商: INTERSIL CORP
元件分類: Buffer和線驅動
英文描述: 3.3V, ±15kV ESD Protected, Two Port, Dual Protocol (RS-232/RS-485) Transceivers; Temperature Range: -40°C to 85°C; Package: 28-SSOP
中文描述: DUAL LINE TRANSCEIVER, PDSO28
封裝: ROHS COMLIANT, PLASTIC, MO-150-AHB, SSOP-28
文件頁數: 10/26頁
文件大?。?/td> 946K
代理商: ISL3332IAZ
18
FN6362.0
May 27, 2008
All but 10uA of SHDN supply current (ICC plus IL) is due to
control input (ON, LB, SP, DE, DEN) pull-up resistors
(~11
μA/resistor), so SHDN supply current varies depending
on the ISL333X configuration. The spec tables indicate the
SHDN currents for configurations that optimize these
currents. For example, in RS-232 mode the SP pins aren’t
used, so if both ports are configured for RS-232, floating or
tying the SP pins high minimizes SHDN current. Likewise in
RS-485 mode, the drivers are disabled in SHDN, so driving
the DE and DEN pins high during this time also reduces the
supply current.
When enabling from SHDN in RS-232 mode, allow at least
25
μs for the charge pumps to stabilize before transmitting
data. The charge pumps aren’t used in RS-485 mode, so the
transceiver is ready to send or receive data in less than 2s,
which is much faster than competing devices that require the
charge pump for all modes of operation.
Internal Loopback Mode
Driving the LB pin low places both ports in the loopback
mode, a mode that facilitates implementing board level self
test functions. In loopback, internal switches disconnect the
Rx inputs from the Rx outputs, and feed back the Tx outputs
to the appropriate Rx output. This way the data driven at the
Tx input appears at the corresponding Rx output (refer to
remain connected to their terminals, so the external loads
are reflected in the loopback performance. This allows the
loopback function to potentially detect some common bus
faults such as one or both driver outputs shorted to GND, or
outputs shorted together.
Note that the loopback mode uses an additional set of
receivers, as shown in the “Typical Operating Circuits”.
These loopback receivers are not standards compliant, so
the loopback mode can’t be used to implement a half-duplex
RS-485 transceiver.
If loopback won’t be utilized, the pin can be left disconnected
(thanks to the internal pull-up), or it should be connected to
VCC (VL for the QFN), through a 1kΩ resistor.
ISL3333 (QFN Package) Special Features
Logic Supply (VL Pin)
The ISL3333 (QFN) includes a VL pin that powers the logic
inputs (Tx inputs and control pins) and Rx outputs. These
pins interface with “l(fā)ogic” devices such as UARTs, ASICs,
and
μcontrollers, and today most of these devices use power
supplies significantly lower than 3.3V. Thus, a 3.3V output
level from a 3.3V powered dual protocol IC might seriously
overdrive and damage the logic device input. Similarly, the
logic device’s low VOH might not exceed the VIH of a 3.3V
powered dual protocol input. Connecting the VL pin to the
power supply of the logic device (Figure 12) limits the
ISL3333’s Rx output VOH to VL (Figure 15), and reduces the
Tx and control input switching points to values compatible
with the logic device output levels. Tailoring the logic pin
input switching points and output levels to the supply voltage
of the UART, ASIC, or
μcontroller eliminates the need for a
level shifter/translator between the two ICs.
VL can be anywhere from VCC down to 1.2V, but the input
switching points may not provide enough noise margin when
VL < 1.5V. Table 5 indicates typical VIH and VIL values for
various VL voltages so the user can ascertain whether or not
a particular VL voltage meets his needs.
Note: With VL ≤ 1.6V, the ISL3333 may not operate at the full
data rate unless the logic signal VIL is at least 0.2V below
the typical value listed in Table 5.
The VL supply current (IL) is typically less than 80μA, even in
the worst case configuration, as shown in Figures 20 and 21.
With the Rx outputs unloaded, all of the DC VL current is due
to inputs with internal pull-up resistors (DE, DEN, SP, LB,
TABLE 5. VIH AND VIL vs. VL FOR VCC = 3.3V
VL (V)
VIH (V)
VIL (V)
1.2
0.85
0.26
1.5
0.9
0.5
1.8
0.9
0.73
2.3
1.2
1.0
2.7
1.4
1.3
3.3
1.8
1.7
FIGURE 12. USING VL PIN TO ADJUST LOGIC LEVELS
GND
RXD
TXD
VCC = +2V
UART/PROCESSOR
GND
RA
DY
VCC = +3.3V
ISL3332
VOH ≤ 2
VOH = 3.3V
VIH ≥ 2
ESD
DIODE
GND
RXD
TXD
VCC = +2V
UART/PROCESSOR
GND
RA
DY
VCC = +3.3V
ISL3333
VOH ≤ 2
VOH = 2V
VIH = 1V
ESD
DIODE
VL
ISL3332, ISL3333
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