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參數(shù)資料
| 型號： | ISL3152EIBZ |
| 廠商： | Intersil |
| 文件頁數(shù)： | 22/22頁 |
| 文件大?。?/td> | 0K |
| 描述： | TXRX ESD 5V RS-485/422 8-SOIC |
| 標準包裝： | 98 |
| 類型： | 收發(fā)器 |
| 驅動器/接收器數(shù)： | 1/1 |
| 規(guī)程： | RS422，RS485 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 8-SOICN |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 1240 (CN2011-ZH PDF) |
9
FN6363.2
July 30, 2009
Receiver Skew | tPLH - tPHL |tSKD
(Figure 5)
Full
-
2.5
5
ns
Receiver Enable to Output
Low
tZL
RL = 1kΩ, CL = 15pF, SW = VCC
(Figure 6), (Note 10)
Full
-
8
15
ns
Receiver Enable to Output
High
tZH
RL = 1kΩ, CL = 15pF, SW = GND
(Figure 6), (Note 10)
Full
-
7
15
ns
Receiver Disable from
Output Low
tLZ
RL = 1kΩ, CL = 15pF, SW = VCC
(Figure 6)
Full
-
8
15
ns
Receiver Disable from
Output High
tHZ
RL = 1kΩ, CL = 15pF, SW = GND
(Figure 6)
Full
-
8
15
ns
Time to Shutdown
tSHDN
(Note 11)
Full
60
160
600
ns
Receiver Enable from
Shutdown to Output High
tZH(SHDN) RL = 1kΩ, CL = 15pF, SW = GND
(Figure 6), (Notes 11, 13)
Full
-
200
ns
Receiver Enable from
Shutdown to Output Low
tZL(SHDN) RL = 1kΩ, CL = 15pF, SW = VCC
(Figure 6), (Notes 11, 13)
Full
-
200
ns
NOTES:
6. All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground
unless otherwise specified.
7. Supply current specification is valid for loaded drivers when DE = 0V.
8. Applies to peak current. See “Typical Performance Curves” beginning on page 14 for more information.
9. Keep RE = 0 to prevent the device from entering SHDN.
10. The RE signal high time must be short enough (typically <100ns) to prevent the device from entering SHDN.
11. Transceivers are put into shutdown by bringing RE high and DE low. If the inputs are in this state for less than 60ns, the parts
are guaranteed not to enter shutdown. If the inputs are in this state for at least 600ns, the parts are guaranteed to have entered
shutdown. See “Low Power Shutdown Mode” on page 13.
12. Keep RE = VCC, and set the DE signal low time >600ns to ensure that the device enters SHDN.
13. Set the RE signal high time >600ns to ensure that the device enters SHDN.
14. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established
by characterization and are not production tested.
15. See Figure 8 for more information, and for performance over-temperature.
16. Tested according to TIA/EIA-485-A, Section 4.2.6 (±100V for 15s at a 1% duty cycle).
17. Limits established by characterization and are not production tested.
Test Circuits and Waveforms
FIGURE 1A. VOD AND VOC
FIGURE 1B. VOD WITH COMMON MODE LOAD
FIGURE 1. DC DRIVER TEST CIRCUITS
Electrical Specifications Test Conditions: VCC = 4.5V to 5.5V; Unless Otherwise Specified. Typicals are at VCC = 5V,
TA =+25°C (Note6). Boldface limits apply over the operating temperature range,
-40°C to +85°C. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
TEMP
(°C)
MIN
(Note 14)
TYP
MAX
(Note 14) UNITS
D
DE
DI
VCC
VOD
VOC
RL/2
Z
Y
D
DE
DI
VCC
VOD
375Ω
Z
Y
RL = 60Ω
VCM
-7V TO +12V
ISL3150E, ISL3152E, ISL3153E, ISL3155E, ISL3156E, ISL3158E
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