
13
FN6177.2
September 3, 2009
TABLE 4. IDENTIFICATION BYTE FORMAT
1010
A2
A1
A0
R/W
(MSB)
(LSB)
Logic values at pins A2, A1, and A0 respectively
SDA
SCL
START
DATA
STOP
STABLE
CHANGE
DATA
STABLE
FIGURE 16. VALID DATA CHANGES, START AND STOP CONDITIONS
SDA OUTPUT FROM
TRANSMITTER
SDA OUTPUT FROM
RECEIVER
8
1
9
START
ACK
SCL FROM
MASTER
HIGH IMPEDANCE
FIGURE 17. ACKNOWLEDGE RESPONSE FROM RECEIVER
HIGH IMPEDANCE
S
T
A
R
T
S
T
O
P
IDENTIFICATION
BYTE
ADDRESS
BYTE
DATA
BYTE
A
C
K
SIGNALS FROM
THE MASTER
SIGNALS FROM
THE SLAVE
A
C
K
1
0
1
00
A
C
K
WRITE
SIGNAL AT SDA
00 0 0
A0
A1
A2
0
FIGURE 18. BYTE WRITE SEQUENCE
ISL22346