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參數(shù)資料
| 型號(hào)： | ISD5008EYI |
| 廠商： | Nuvoton Technology Corporation of America |
| 文件頁數(shù)： | 25/54頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC VOICE REC/PLAY 4-8MIN 28-TSOP |
| 標(biāo)準(zhǔn)包裝： | 234 |
| 系列： | ISD5008 |
| 接口： | SPI/Microwire |
| 濾波器通頻帶： | 1.7 ~ 3.4kHz |
| 持續(xù)時(shí)間： | 4-8 分鐘 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-TSSOP（0.465"，11.8mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-TSOP |
| 配用： | ISD-ES511-ND - EVALUATION SYSTEM FOR ISD5100 ISD-ES501-ND - EVALUATION SYSTEM FOR ISD5008 |
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ISD5008
Publication Release Date: Oct 31 2008
- 31 -
Revision 1.2
er element and also powers
con
the power up state of the
the
should be set to a ONE to power down the stage.
S2M0 and S2M1 control the SUM2 mixer. These are bits D7 and D8 in CFG1
and bits D5 and D6 in CFG1 respectively. All 4 bits should be set to a ONE to power down the
4.
controls the power up state of the FILTER stage in
up state of the AGC amplifier.
a ONE to power down the stage.
6. Don’t Care bits—The following stages are not used in Feed Through Mode. Their bits may be
ar bits D11 and D12 respectively in CFG0. They control the
AUX IN amplifier gain setting.
c. Bits FLD0 and FLD1 are bits D2 and D3 respectively in CFG1. They control the
rate and filter band pass setting.
nd D13 of CFG1. They control the
CFG0 = 0100 0100 0000 1011 (hex 4408)
Sin
registers must be loaded in this order. The internal set up for both registers will take effect
synchronously with the rising edge of
configures it for it’s higher gain setting for use with a piezo speak
down the AUX output stage.
The status of the rest of the functions in the ISD5008 chip must be defined before the
figuration registers settings are updated:
1. Power down the Volume Control Element—Bit VLPD controls
Volume Control. This is bit D0 fo CFG0 and it should be set to a ONE to power down
statge.
2. Power down the AUX IN amplifier—Bit AXPD controls the power up state of the AUX IN input
amplifier. This is bit D10 of CFG0 and it
3. Power down the SUM1 and SUM2 Mixer amplifiers—Bits S1M0 and S1M1 control the SUM
mixer and bits
stage.
Power down the FILTER stage
—Bit FLPD
hould be set to a ONE to power down the stage.
the device. This is bit D0 in CFG1 and s
5. Power down the AGC amplifier—Bit AGPD controls the power
This is bit D0 in CFG1 and should be set to
set to either level. In this example we will set all the following bits to ZERO.
a. Bit INS0, bit D9 of CFG0 controls the Input Source Mux.
b. Bits AXG0 and AXG1
e
sample
d. Bit FLS0 is bit D4 in CFG1. It controls the FILTER MUX.
e. Bits S1S0 and S1S1 are bits D9 and D10 of CFG1. They control the SUM1 MUX.
f.
Bits VOL0, VOL1 and VOL2 are bits D11, D12 a
setting of the Volume Control.
g. Bits VLS0 and VLS1 are bits D14 and D15 of CFG1. They control the Volume Control
Mux.
The end result of the above set up is:
and
CFG1 = 0000 0001 1110 0011 (hex 01E3)
ce both registers are being loaded, CFG0 is loaded followed by the loading of CFG1. These two
SS
.
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相關(guān)代理商/技術(shù)參數(shù) |
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| ISD5008P | 功能描述:IC VOICE REC/PLAY 4-8MIN 28-DIP RoHS:否 類別:集成電路 (IC) >> 接口 - 語音錄制和重放 系列:ISD5008 標(biāo)準(zhǔn)包裝:14 系列:- 接口:串行 濾波器通頻帶:1.7kHz 持續(xù)時(shí)間:8 ~ 32 秒 安裝類型:通孔 封裝/外殼:28-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:28-PDIP 其它名稱:90-21300+000 |
| ISD5008PY | 功能描述:IC VOICE REC/PLAY 4-8MIN 28-DIP RoHS:是 類別:集成電路 (IC) >> 接口 - 語音錄制和重放 系列:ISD5008 標(biāo)準(zhǔn)包裝:14 系列:- 接口:串行 濾波器通頻帶:1.7kHz 持續(xù)時(shí)間:8 ~ 32 秒 安裝類型:通孔 封裝/外殼:28-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:28-PDIP 其它名稱:90-21300+000 |
| ISD5008S | 功能描述:IC VOICE REC/PLAY 4-8MIN 28-SOIC RoHS:否 類別:集成電路 (IC) >> 接口 - 語音錄制和重放 系列:ISD5008 標(biāo)準(zhǔn)包裝:14 系列:- 接口:串行 濾波器通頻帶:1.7kHz 持續(xù)時(shí)間:8 ~ 32 秒 安裝類型:通孔 封裝/外殼:28-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:28-PDIP 其它名稱:90-21300+000 |
| ISD5008SD | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SINGLE CHIP VOICE RECORD PLAYBACK DEVICE 4-, 5-, 6-, AND 8- MINUTE DURATIONS |
| ISD5008SERIES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single-Chip Voice Record/Playback Device |
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