參數(shù)資料
型號(hào)： ISD5008
廠商： WINBOND ELECTRONICS CORP
英文描述： Single-Chip Voice Record/Playback Device（Single-chip Durations of 4 to 8 minutes)(單片的錄音/錄音重放器(單片信息存儲(chǔ)持續(xù)時(shí)間4到8分鐘）)
中文描述： 單芯片語(yǔ)音記錄/播放設(shè)備（單4至8分鐘芯片工期）（單片的錄音/錄音重放器（單片信息存儲(chǔ)持續(xù)時(shí)間4到8分鐘））
文件頁(yè)數(shù)： 25/46頁(yè)
文件大?。?/td> 1115K
代理商： ISD5008
ISD5008 Product
22
Voice Solutions in Silicon
To select this mode, the following control bits must
be configured in the ISD5008 configuration regis-
ters. To set up the transmit path:
1.
Select the FTHRU path through the ANA
OUT MUX—
Bits AOS0, AOS1 and AOS2 con-
trol the state of the ANAOUT MUX. These are
the D6, D7 and D8 bits respectively of Con-
figuration Register 0 (CFG0) and they
should all be ZERO to select the FTHRU path.
2.
Power up the ANA OUT amplifier
—Bit AOPD
controls the power up state of ANA OUT.
This is bit D5 of CFG0 and it should be a
ZERO to power up the amplifier.
To set up the receive path:
1.
Set up the ANA IN amplifier for the correct
gain
—Bits AIG0 and AIG1 control the gain
settings of this amplifier. These are bits D14
and D15 respectively of CFG0. The input
level at this pin determines the setting of this
gain stage. Table 4 will help determine this
setting. In this example we will assume that
the peak signal never goes above 1 volt p-
p single ended. That would enable us to use
the 9dB attenuation setting, or where D14 is
ONE and D15 is ZERO.
2.
Power up the ANA IN amplifier
—Bit AIPD
controls the power up state of ANA IN. This
is bit D13 of CFG0 and should be a ZERO to
power up the amplifier.
3.
Select the ANA IN path through the OUTPUT
MUX
—Bits OPS0 and OPS1 control the state
of the OUTPUT MUX. These are bits D3 and
D4 respectively of CFG0 and they should
be set to the state where D3 is ONE and D4
is ZERO to select the ANA IN path.
4.
Power up the Speaker Amplifier
—Bits OPA0
and OPA1 control the state of the Speaker
and AUX amplifiers. These are bits D1 and
D2 respectively of CFG0. They should be set
to the state where D1 is ONE and D2 is ZERO.
This powers up the Speaker Amplifier and
configures it for it’s higher gain setting for
use with a piezo speaker element and also
powers down the AUX output stage.
The status of the rest of the functions in the ISD5008
chip must be defined before the configuration
registers settings are updated:
1.
Power down the Volume Control Ele-
ment
—Bit VLPD controls the power up state
of the Volume Control. This is bit D0 of CFG0
and it should be set to a ONE to power
down this stage.
2.
Power down the AUX IN amplifier
—Bit
AXPD controls the power up state of the
AUX IN input amplifier. This is bit D10 of CFG0
and it should be set to a ONE to power
down this stage.
3.
Power down the SUM1 and SUM2 Mixer
amplifiers
—Bits S1M0 and S1M1 control the
SUM1 mixer and bits S2M0 and S2M1 control
the SUM2 mixer. These are bits D7 and D8 in
CFG1 and bits D5 and D6 in CFG1 respec-
tively. All 4 bits should be set to a ONE to
power down these two amplifiers.
4.
Power down the FILTER stage
—Bit FLPD
controls the power up state of the FILTER
stage in the device. This is bit D1 in CFG1
and should be set to a ONE to power down
the stage.
5.
Power down the AGC amplifier
—Bit AGPD
controls the power up state of the AGC
amplifier. This is bit D0 in CFG1 and should
be set to a ONE to power down this stage.
6.
Don’t Care bits
—The following stages are
not used in Feed Through Mode. Their bits
may be set to either level. In this example
we will set all the following bits to a ZERO.
(a). Bit INS0, bit D9 of CFG0 controls the In-
put Source Mux. (b). Bits AXG0 and AXG1
are bits D11 and D12 respectively in CFG0.
They control the AUX IN amplifier gain set-
ting. (c). Bits FLD0 and FLD1 are bits D2 and
D3 respectively in CFG1. They control the
sample rate and filter band pass setting.
(d). Bit FLS0 is bit D4 in CFG1. It controls the
FILTER MUX. (e). Bits S1S0 and S1S1 are bits
D9 and D10 of CFG1. They control the SUM1
MUX. (f). Bits VOL0, VOL1 and VOL2 are bits
相關(guān)PDF資料
PDF描述
ISD5100 SINGLE-CHIP 1 TO 16 MINUTES DURATION VOICE RECORD/PLAYBACK DEVICES WITH DIGITAL STORAGE CAPABILITY
ISD5116 Single-Chip Voice Record/Playback Device Up to 16-Minute Duration with Digital Storage Capability
ISD5116E Single-Chip Voice Record/Playback Device Up to 16-Minute Duration with Digital Storage Capability
ISD5116ED Single-Chip Voice Record/Playback Device Up to 16-Minute Duration with Digital Storage Capability
ISD5116EI Single-Chip Voice Record/Playback Device Up to 16-Minute Duration with Digital Storage Capability
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ISD5008E 功能描述:IC VOICE REC/PLAY 4-8MIN 28-TSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 語(yǔ)音錄制和重放 系列:ISD5008 標(biāo)準(zhǔn)包裝:14 系列:- 接口:串行 濾波器通頻帶:1.7kHz 持續(xù)時(shí)間:8 ~ 32 秒 安裝類型:通孔 封裝/外殼:28-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:28-PDIP 其它名稱:90-21300+000
ISD5008ED 功能描述:IC VOICE REC/PL 4-8MIN EX 28TSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 語(yǔ)音錄制和重放 系列:ISD5008 標(biāo)準(zhǔn)包裝:14 系列:- 接口:串行 濾波器通頻帶:1.7kHz 持續(xù)時(shí)間:8 ~ 32 秒 安裝類型:通孔 封裝/外殼:28-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:28-PDIP 其它名稱:90-21300+000
ISD5008EDR 功能描述:IC VOICE REC/PL 4-8MIN EX 28TSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 語(yǔ)音錄制和重放 系列:ISD5008 標(biāo)準(zhǔn)包裝:14 系列:- 接口:串行 濾波器通頻帶:1.7kHz 持續(xù)時(shí)間:8 ~ 32 秒 安裝類型:通孔 封裝/外殼:28-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:28-PDIP 其它名稱:90-21300+000
ISD5008EI 功能描述:IC VOICE REC/PL 4-8MIN IN 28TSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 語(yǔ)音錄制和重放 系列:ISD5008 標(biāo)準(zhǔn)包裝:14 系列:- 接口:串行 濾波器通頻帶:1.7kHz 持續(xù)時(shí)間:8 ~ 32 秒 安裝類型:通孔 封裝/外殼:28-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:28-PDIP 其它名稱:90-21300+000
ISD5008EIR 功能描述:IC VOICE REC/PL 4-8MIN IN 28TSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 語(yǔ)音錄制和重放 系列:ISD5008 標(biāo)準(zhǔn)包裝:14 系列:- 接口:串行 濾波器通頻帶:1.7kHz 持續(xù)時(shí)間:8 ~ 32 秒 安裝類型:通孔 封裝/外殼:28-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:28-PDIP 其它名稱:90-21300+000
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