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參數資料
| 型號： | IS42S16400B-7T |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM |
| 中文描述： | 1梅格位× 16位× 4銀行（64兆位）同步動態(tài)RAM |
| 文件頁數： | 7/55頁 |
| 文件大?。?/td> | 472K |
| 代理商： | IS42S16400B-7T |
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IS42S16400B
ISSI
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. D
02/10/05
7
TRUTH TABLE – CURRENT STATE BANK n, COMMAND TO BANK n
(1-6)
CURRENT STATE
COMMAND (ACTION)
CS
RAS
CAS WE
Any
COMMAND INHIBIT
(NOP/Continue previous operation)
H
X
X
X
NO OPERATION
(NOP/Continue previous operation)
L
H
H
H
Idle
ACTIVE (Select and activate row)
L
L
H
H
AUTO REFRESH
(7)
L
L
L
H
LOAD MODE REGISTER
(7)
L
L
L
L
PRECHARGE
(11)
L
L
H
L
Row Active
READ (Select column and start READ burst)
(10)
L
H
L
H
WRITE (Select column and start WRITE burst)
(10)
L
H
L
L
PRECHARGE (Deactivate row in bank or banks)
(8)
L
L
H
L
Read
READ (Select column and start new READ burst)
(10)
L
H
L
H
(Auto
WRITE (Select column and start WRITE burst)
(10)
L
H
L
L
Precharge
PRECHARGE (Truncate READ burst, start PRECHARGE)
(8)
L
L
H
L
Disabled)
BURST TERMINATE
(9)
L
H
H
L
Write
READ (Select column and start READ burst)
(10)
L
H
L
H
(Auto
WRITE (Select column and start new WRITE burst)
(10)
L
H
L
L
Precharge
PRECHARGE (Truncate WRITE burst, start PRECHARGE)
(8)
L
L
H
L
Disabled)
BURST TERMINATE
(9)
L
H
H
L
TRUTH TABLE – CKE
(1-4)
CURRENT STATE
COMMANDn
ACTIONn
CKEn-1
CKEn
Power-Down
X
Maintain Power-Down
L
L
Self Refresh
X
Maintain Self Refresh
L
L
Clock Suspend
X
Maintain Clock Suspend
L
L
Power-Down
(5)
COMMAND INHIBIT or NOP
Exit Power-Down
L
H
Self Refresh
(6)
COMMAND INHIBIT or NOP
Exit Self Refresh
L
H
Clock Suspend
(7)
X
Exit Clock Suspend
L
H
All Banks Idle
COMMAND INHIBIT or NOP
Power-Down Entry
H
L
All Banks Idle
AUTO REFRESH
Self Refresh Entry
H
L
Reading or Writing
VALID
Clock Suspend Entry
H
L
See TRUTH TABLE – CURRENT STATE BANK n, COMMAND TO BANK n
H
H
NOTES:
1. CKEn is the logic state of CKE at clock edge n CKEn-1 was the state of CKE at the previous clock edge.
2. Current state is the state of the SDRAM immediately prior to clock edge n
3. COMMANDn is the command registered at clock edge n and ACTONn is a result of COMMANDn.
4. All states and sequences not shown are illegal or reserved.
5. Exiting power-down at clock edge nwill put the device in the all banks idle state in time for clock edge n+1
(provided that t
CKS
is met)
.
6. Exiting self refresh at clock edge nwill put the device in all banks idle state once t
XSR
is met. COMMAND INHIBIT or NOP commands
should be issued on clock edges occurring during the t
XSR
period. A minimum of two NOP commands must be sent during t
XSR
period.
7. After exiting clock suspend at clock edge n the device will resume operation and recognize the next command at clock edge n+1
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PDF描述 |
|---|---|
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相關代理商/技術參數 |
參數描述 |
|---|---|
| IS42S16400B-7TI | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IS42S16400B-7TL | 制造商:Integrated Silicon Solution Inc 功能描述:64M, 3.3V SDRAM 4M X 16 143MHZ TSOP |
| IS42S16400B-7TLI | 制造商:Integrated Silicon Solution Inc 功能描述: |
| IS42S16400B-7TLI-TR | 制造商:Integrated Silicon Solution Inc 功能描述: |
| IS42S16400B-7TL-TR | 制造商:Integrated Silicon Solution Inc 功能描述: |
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