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參數(shù)資料
| 型號： | IS42S16400B-6TL |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM |
| 中文描述： | 1梅格位× 16位× 4銀行（64兆位）同步動態(tài)RAM |
| 文件頁數(shù)： | 19/55頁 |
| 文件大?。?/td> | 472K |
| 代理商： | IS42S16400B-6TL |
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IS42S16400B
ISSI
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. D
02/10/05
19
CLK
CKE
HIGH - Z
ROW ADDRESS
BANK ADDRESS
CS
RAS
CAS
WE
A0-A11
BA0, BA1
Activating Specific Row Within Specific Bank
DON'T CARE
CLK
COMMAND
ACTIVE
NOP
NOP
t
RCD
T0
T1
T2
T3
T4
READ or
WRITE
OPERATION
BANK/ROW ACTIVATION
Before any READ or WRITE commands can be issued to
a bank within the SDRAM, a row in that bank must be
“opened.”
This is accomplished via the ACTIVE command,
which selects both the bank and the row to be activated
(see
Activating Specific Row Within Specific Bank
).
After opening a row
(issuing an ACTIVE command)
, a READ
or WRITE command may be issued to that row, subject to
the t
RCD
specification. Minimum t
RCD
should be divided by
the clock period and rounded up to the next whole number
to determine the earliest clock edge after the ACTIVE
command on which a READ or WRITE command can be
entered. For example, a t
RCD
specification of 20ns with a
125 MHz clock (8ns period) results in 2.5 clocks, rounded
to 3. This is reflected in the following example, which
covers any case where 2 < [t
RCD
(MIN)/t
CK
]
≤
3. (The
same procedure is used to convert other specification
limits from time units to clock cycles).
A subsequent ACTIVE command to a different row in the
same bank can only be issued after the previous active
row has been “closed” (precharged). The minimum time
interval between successive ACTIVE commands to the
same bank is defined by t
RC
.
A subsequent ACTIVE command to another bank can be
issued while the first bank is being accessed, which
results in a reduction of total row-access overhead. The
minimum time interval between successive ACTIVE com-
mands to different banks is defined by t
RRD
.
Example: Meeting t
RCD
(MIN) when 2
<
[t
RCD
(min)/t
CK
]
≤
3
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| IS42S16400B-6TLI | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IS42S16400B-6TL-TR | 制造商:Integrated Silicon Solution Inc 功能描述: |
| IS42S16400B-7T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IS42S16400B-7TI | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IS42S16400B-7TL | 制造商:Integrated Silicon Solution Inc 功能描述:64M, 3.3V SDRAM 4M X 16 143MHZ TSOP |
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