參數(shù)資料
型號: IS32WV10008ALL-85BI
廠商: INTEGRATED SILICON SOLUTION INC
元件分類: SRAM
英文描述: 1M X 8 PSEUDO STATIC RAM, 85 ns, PBGA48
封裝: 6 X 8 MM, BGA-48
文件頁數(shù): 11/12頁
文件大?。?/td> 53K
代理商: IS32WV10008ALL-85BI
IS32WV10008ALL,
IS32WV10008BLL
ISSI
8
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00A
08/15/02
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)
55 ns
70 ns
85 ns
100 ns
Symbol
Parameter
Min. Max.
Min.Max.
Min. Max.
Unit
tWC
Write Cycle Time
55
70
85
100
ns
tSCS1/tSCS2 CS1/CS2 to Write End
45
60
65
70
ns
tAW
Address Setup Time to Write End
45
60
65
70
ns
tHA
Address Hold from Write End
0
0
0
0
ns
tSA
Address Setup Time
0
0
0
0
ns
tPWE
WE Pulse Width
40
50
60
60
ns
tSD
Data Setup to Write End
25
30
35
40
ns
tHD
Data Hold from Write End
0
0
0
0
ns
tHZWE(3)
WE LOW to High-Z Output
20
20
20
20
ns
tLZWE(3)
WE HIGH to Low-Z Output
5
5
5
5
ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V, input pulse levels of 0.4V to 1.4V
and output loading specified in Figure 1.
2. The internal write time is defined by the overlap of
CS1 LOW, CS2 HIGH and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but
any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the
write.
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
AC WAVEFORMS
WRITE CYCLE NO. 1 (
CS1/CS2 Controlled, OE = HIGH or LOW)
DATA-IN VALID
DATA UNDEFINED
tWC
tSCS1
tSCS2
tAW
tHA
tPWE
tHZWE
HIGH-Z
tLZWE
tSA
tSD
tHD
ADDRESS
CS1
CS2
WE
DOUT
DIN
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