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參數(shù)資料
| 型號： | IRU3047CW |
| 廠商： | International Rectifier |
| 元件分類： | 基準電壓源/電流源 |
| 英文描述： | DUAL SYNCHRONOUS PWM CONTROLLER WITH CURRENT SHARING CIRCUITRY AND LDO CONTROLLER |
| 中文描述： | 雙同步PWM控制器，帶有均流電路和LDO控制器 |
| 文件頁數(shù)： | 10/19頁 |
| 文件大?。?/td> | 141K |
| 代理商： | IRU3047CW |
10
Rev. 1.0
09/09/02
IRU3047
www.irf.com
The pole sets to one half of switching frequency which
results in the capacitor C
POLE:
1
For a general solution for unconditionally stability for any
type of output capacitors, in a wide range of ESR values
we should implement local feedback with a compensa-
tion network. The typically used compensation network
for voltage-mode controller is shown in Figure 7.
Figure 7 - Compensation network with local
feedback and its asymptotic gain plot.
In such configuration, the transfer function is given by:
1 -
g
m
Z
f
1 +
g
m
Z
IN
The error amplifier gain is independent of the transcon-
ductance under the following condition:
g
m
Z
f
>> 1 and
g
m
Z
IN
>>1 ---(15)
By replacing Z
IN
and Z
f
according to figure 7, the trans-
former function can be expressed as:
V
e
V
OUT
=
As known, transconductance amplifier has high imped-
ance (current source) output, therefore, consider should
be taken when loading the E/A output. It may exceed its
source/sink output current capability, so that the ampli-
fier will not be able to swing its output voltage over the
necessary range.
The compensation network has three poles and two ze-
ros and they are expressed as follows:
F
P1
= 0
1
2
π×
R
8
×
C
10
Cross Over Frequency:
The stability requirement will be satisfied by placing the
poles and zeros of the compensation network according
to following design rules. The consideration has been
taken to satisfy condition (15) regarding transconduc-
tance error amplifier.
1)
Select the crossover frequency:
2)
Select R
7
, so that R
7
>>
3)
Place first zero before LC’s resonant frequency pole.
2
g
m
Fo < F
ESR
and Fo
≤
(1/10 ~ 1/6)
×
f
S
F
Z1
75% F
LC
C
11
=
1
2
π ×
F
Z1
×
R
7
C
POLE
=
π ×
R
4
×
f
S
-
1
C
9
1
π ×
R
4
×
f
S
For F
P
<<f
S
2
1
π×
C
10
×
(R
6
+ R
8
)
F
Z2
= 2
1
2
π×
C
10
×
R
6
F
Z1
=
1
2
π×
R
7
×
C
11
F
P3
=
2
π×
R
7
×
1
F
P2
=
1
2
π×
R
7
×
C
12
C
12
×
C
11
C
12
+C
11
V
OUT
V
REF
R
5
R
6
R
8
C
10
C
12
C
11
R
7
Ve
F
Z
1
F
Z
2
F
P
2
F
P
3
Z
f
Z
IN
Frequency
Gain(dB)
H(s) dB
Fb1
E/A1
Comp1
H(s)=
sR
6
(C
12
+C
11
)
1+sR
7
×
(1+sR
8
C
10
)
C
12
+C
11
[ ( )]
1 (1+sR
7
C
11
)
×
[1+sC
10
(R
6
+R
8
)]
×
C
12
C
11
Where:
V
IN
= Maximum Input Voltage
V
OSC
= Oscillator Ramp Voltage
Lo = Output Inductor
Co = Total Output Capacitors
F
O1
= R
7
×
C
10
×
×
V
IN
V
OSC
1
2
π×
Lo
×
Co
---(16)
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