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| 型號(hào)： | IRU3005CW |
| 文件頁(yè)數(shù)： | 10/14頁(yè) |
| 文件大小： | 83K |
| 代理商： | IRU3005CW |
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4-12
Rev. 1.2
12/8/00
IRU3004, IRU3005
APPLICATION INFORMATION
An example of how to calculate the components for the
application circuit is given below.
Assuming, two sets of output conditions that this regu-
lator must meet,
a) Vo=2.8V, Io=14.2A,
Vo=185mV,
Io=14.2A
b) Vo=2V, Io=14.2A,
Vo=140mV,
Io=14.2A
The regulator design will be done such that it meets the
worst case requirement of each condition.
Output Capacitor Selection
The first step is to select the output capacitor. This is
done primarily by selecting the maximum ESR value
that meets the transient voltage budget of the total
Vo
specification. Assuming that the regulators DC initial
accuracy plus the output ripple is 2% of the output volt-
age, then the maximum ESR of the output capacitor is
calculated as:
ESR
≤
=
100
14 2
7
.
m
The Sanyo MVGX series is a good choice to achieve
both the price and performance goals. The 6MV1500GX,
1500
μ
F, 6.3V has an ESR of less than 36m
typical.
Selecting 6 of these capacitors in parallel has an ESR
of
≈
6m
which achieves our low ESR goal.
Other type of Electrolytic capacitors from other manu-
facturers to consider are the Panasonic FA series or the
Nichicon PL series.
Reducing the Output Capacitors Using Voltage Level
Shifting Technique
The trace resistance or an external resistor from the output
of the switching regulator to the Slot 1 can be used to
the circuit advantage and possibly reduce the number of
output capacitors, by level shifting the DC regulation point
when transitioning from light load to full load and vice
versa. To accomplish this, the output of the regulator is
typically set about half the DC drop that results from
light load to full load. For example, if the total resistance
from the output capacitors to the Slot 1 and back to the
GND pin of the device is 5m
and if the total
I, the
change from light load to full load is 14A, then the output
voltage measured at the top of the resistor divider which
is also connected to the output capacitors in this case,
must be set at half of the 70mV or 35mV higher than the
DAC voltage setting. This intentional voltage level
shifting during the load transient eases the requirement
for the output capacitor ESR at the cost of load regula-
tion. One can show that the new ESR requirement eases
up by half the total trace resistance. For example, if the
ESR requirement of the output capacitors without volt-
age level shifting must be 7m
,
then after level shifting
the new ESR will only need to be 9.5m
if the trace
resistance is 5m
(7+5/2=9.5). However, one must be
careful that the combined “voltage level shifting” and the
transient response is still within the maximum tolerance
of the Intel specification. To insure this, the maximum
trace resistance must be less than:
Rs
≤
2(Vspec - 0.02*Vo -
Vo)/
I
Where :
Rs=Total maximum trace resistance allowed
Vspec=Intel total voltage spec
Vo=Output voltage
Vo=Output ripple voltage
I=load current step
For example, assuming:
Vspec=
±
140 mV=
±
0.1V for 2V output
Vo=2V
Vo=assume 10mV=0.01V
I=14.2A
Then the Rs is calculated to be:
Rs
≤
2(0.140 - 0.02*2 - 0.01)/14.2=12.6m
However, if a resistor of this value is used, the maximum
power dissipated in the trace (or if an external resistor is
being used) must also be considered. For example if
Rs=12.6m
,
the
power
(Io^2)*Rs=(14.2^2)*12.6=2.54W. This is a lot of power to
be dissipated in a system. So, if the Rs=5m
, then the
power dissipated is about 1W which is much more ac-
ceptable. If level shifting is not implemented, then the
maximum output capacitor ESR was shown previously
to be 7m
which translated to
≈
6 of the 1500
μ
F,
6MV1500GX type Sanyo capacitors. With Rs=5m
, the
maximum ESR becomes 9.5m
which is equivalent to
≈
4 caps. Another important consideration is that if a
trace is being used to implement the resistor, the power
dissipated by the trace increases the case temperature
of the output capacitors which could seriously effect the
life time of the output capacitors.
dissipated
is
Output Inductor Selection
The output inductance must be selected such that un-
der low line and the maximum output voltage condition,
the inductor current slope times the output capacitor
ESR is ramping up faster than the capacitor voltage is
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