參數(shù)資料
型號(hào)： IRS2336D
廠商： International Rectifier
英文描述： HIGH VOLTAGE 3 PHASE GATE DRIVER IC
中文描述： 3相高壓柵極驅(qū)動(dòng)器集成電路
文件頁(yè)數(shù)： 26/45頁(yè)
文件大小： 952K
代理商： IRS2336D
IRS2336xD Family
www.irf.com
2007 International Rectifier
26
Figure 15: Programming over-temperature
protection
Figure 16: Using over-current protection and over-
temperature protection
Truth Table: Undervoltage lockout, ITRIP, and ENABLE
Table 4 provides the truth table for the IRS2336xD. The first line shows that the UVLO for V
CC
has been tripped; the
FAULT output has gone low and the gate drive outputs have been disabled. V
CCUV
is not latched in this case and
when V
CC
is greater than V
CCUV
, the FAULT output returns to the high impedance state.
The second case shows that the UVLO for V
BS
has been tripped and that the high-side gate drive outputs have been
disabled. After V
BS
exceeds the V
BSUV
threshold, HO will stay low until the HVIC input receives a new falling
(IRS2336D) or rising (IRS23364D) transition of HIN. The third case shows the normal operation of the HVIC. The
fourth case illustrates that the ITRIP trip threshold has been reached and that the gate drive outputs have been
disabled and a fault has been reported through the fault pin. In the last case, the HVIC has received a command
through the EN input to shutdown; as a result, the gate drive outputs have been disabled.
VCC
<V
CCUV
15 V
15 V
15 V
15 V
VBS
---
<V
BSUV
15 V
15 V
15 V
ITRIP
---
0 V
0 V
>V
ITRIP
0 V
EN
---
5 V
5 V
5 V
0 V
RCIN
High
High
High
Low
High
FAULT
0
LO
0
LIN
LIN
0
0
HO
0
0
HIN
0
0
UVLO V
CC
UVLO V
BS
Normal operation
ITRIP fault
EN command
High impedance
High impedance
0
High impedance
Table 4: IRS2336xD UVLO, ITRIP, EN, RCIN, & FAULT truth table
Advanced Input Filter
The advanced input filter allows an improvement in the input/output pulse symmetry of the HVIC and helps to reject
noise spikes and short pulses. This input filter has been applied to the HIN, LIN, and EN inputs. The working
principle of the new filter is shown in Figures 17 and 18.
Figure 17 shows a typical input filter and the asymmetry of the input and output. The upper pair of waveforms
(Example 1) show an input signal with a duration much longer then t
FIL,IN
; the resulting output is approximately the
difference between the input signal and t
FIL,IN
. The lower pair of waveforms (Example 2) show an input signal with a
duration slightly longer then t
FIL,IN
; the resulting output is approximately the difference between the input signal and
t
FIL,IN
.
Figure 18 shows the advanced input filter and the symmetry between the input and output. The upper pair of
waveforms (Example 1) show an input signal with a duration much longer then t
FIL,IN
; the resulting output is
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