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參數(shù)資料
| 型號： | IRS2168DSTRPBF |
| 廠商： | International Rectifier |
| 英文描述： | ADVANCED PFC + BALLAST CONTROL IC |
| 中文描述： | 先進PFC的鎮(zhèn)流器控制IC |
| 文件頁數(shù)： | 14/21頁 |
| 文件大小： | 313K |
| 代理商： | IRS2168DSTRPBF |
IRS2168D(S)PbF
www.irf.com Page 14
Run Mode (RUN)
Once V
has exceeded 2/3*V
(V
) for the
second time, the IC enters run mode. CPH continues to
charge up to V
. The operating frequency is at the
minimum frequency (after the ignition ramp) and is
programmed by the external resistor (R
) at the FMIN
pin. Should hard-switching occur at the half-bridge at any
time (open-filament, lamp removal, etc.), the voltage
across the current sensing resistor (R
) will exceed the
internal threshold of 1.2 V (V
) and the fault counter
will begin counting (see Fig. 5). Should the number of
consecutive over-current faults exceed 65 (n
), the
IC will enter fault mode and the HO, LO and PFC gate
driver outputs will be latched low. During run mode, the
end-of-life (EOL) window comparator and the DC bus
undervoltage reset are both enabled.
DC Bus Undervoltage Reset
Should the DC bus decrease too low during a brown-out
line condition or over-load condition, the resonant output
stage to the lamp can shift near or below resonance. This
can produce hard switching at the half- bridge that can
damage the half-bridge switches, or, the DC bus can
decrease too far and the lamp can extinguish. To protect
against this, the V
BUS
pin includes a 3.0 V undervoltage
reset threshold V
. When the IC is in run mode and
the voltage at the V
pin decreases below 3.0 V (V
), V
will be discharged through an internal MOSFET
down to the V
threshold and all gate driver outputs
will be latched low. For proper ballast design, the
designer should set the over-current limit of the PFC
section such that the DC bus does not drop until the AC
line input voltage falls below the minimum rated input
voltage of the ballast (see PFC section). When the PFC
over-current limit is correctly set, the DC bus voltage will
start to decrease when over-current is reached during
low-line conditions. The voltage measured at the V
BUS
pin
will decrease below the internal 3.0 V threshold V
and the ballast will turn off cleanly. The pull-up resistor to
V
CC
(R
) will then turn the ballast on again when the AC
input line voltage increases high enough again where
V
CC
exceeds V
CCUV+
. R
should be set to turn the ballast on
at the minimum specified ballast input voltage and the
PFC over-current should be set somewhere below this
level. This hysteresis will result in clean turn-on and turn-
off of the ballast.
SD/EOL and CS Fault Mode
Should the voltage at the SD/EOL pin exceed 3.0 V
(V
or decrease below 1.0 V (V
) during run
mode, an end-of-life (EOL) fault condition has occurred
and the IC enters fault mode. LO, HO and PFC gate
driver outputs are all latched off in the ‘low’ state. CPH is
discharged to COM for resetting the preheat time and
VCO is discharged to COM for resetting the frequency.
To exit fault mode, V
can be decreased below V
(ballast power off) or the SD pin can be increased above
5.0 V (V
) (lamp removal). Either of these will force
the IC to enter UVLO mode (see State Diagram, page 3).
Once V
CC
is above V
CCUV+
(ballast power on) and SD is
pulled above 5.0 V (V
) and back below 3.0 V (V
)
(lamp re-insertion), the IC will enter preheat mode and
begin oscillating again.
The current sense function will force the IC to enter fault
mode only after the voltage at the CS pin has been
greater than 1.2 V (V
) for 65 (n
) consecutive
cycles of LO. The voltage at the CS pin is AND-ed with
LO (see Fig. 9) so it will work with pulses that occur
during the LO on-time or DC. If the over-current faults
are not consecutive, then the internal fault counter will
count back down each cycle when there is no fault.
Should an over-current fault occur only for a few cycles
and then not occur again, the counter will eventually reset
to zero. The over-current fault counter is enabled during
preheat and run modes and disabled during ignition
mode.
50 Cycles
LO
CS
Run or Preheat Mode
Fault Mode
1.25V
Figure 9:
Fault counter timing diagram
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