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參數(shù)資料
| 型號： | IRS2166DSTRPBF |
| 廠商： | International Rectifier |
| 元件分類： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | PFC + BALLAST CONTROL IC |
| 中文描述： | PFC的鎮(zhèn)流器控制IC |
| 文件頁數(shù)： | 12/20頁 |
| 文件大?。?/td> | 513K |
| 代理商： | IRS2166DSTRPBF |
IRS2166D(S)PbF
www.irf.com
Page 12
The PFC control circuit of the IRS2166D (Fig. 8) only
requires four control pins: VBUS, COMP, ZX and PFC.
The VBUS pin is for sensing the DC bus voltage (via an
external resistor voltage divider), the COMP pin programs
the on-time of M
PFC
and the speed of the feedback loop,
the ZX pin detects when the inductor current discharges
to zero (via a secondary winding from the PFC inductor),
and the PFC pin is the low-side gate driver output for
M
PFC
.
RVBUS1
RVBUS
CCOMP
LPFC
MPFC
RPFC
DFPC
CBUS
(+)
(-)
RZX
PFC
Control
VBUS
COMP
PFC
ZX
COM
DCOMP
Fig. 8:
IRS2166D simplified PFC control circuit
The VBUS pin is regulated against a fixed internal 4.0 V
reference voltage (V
BUSREG
) for regulating the DC bus
voltage (Fig. 9). The feedback loop is performed by an
operational transconductance amplifier (OTA) that sinks
or sources a current to the external capacitor at the
COMP pin. The resulting voltage on the COMP pin sets
the threshold for the charging of the internal timing
capacitor (C1) and therefore programs the on-time of
M
PFC
. During preheat and ignition modes of the ballast
section, the gain of the OTA is set to a high level to raise
the DC bus level quickly and to minimize the transient on
the DC bus which can occur during ignition. During run
mode, the gain is then decreased to a lower level
necessary for achieving high power factor and low THD.
Run Mode Signal
Fault Mode Signal
7
6
1
Q
S
R
Q
2.0V
VBUS
COMP
ZX
7.6V
4.0V
GAIN
OTA1
4.3V
8
PFC
Q
S
R1
R2 Q
COMP3
COMP4
COMP5
RS3
RS4
VCC
M1
WATCH
DOG
TIMER
M2
C1
3.0V
Discharge
VCC to
UVLO-
COMP2
Fig. 9:
IRS2166D detailed PFC control circuit
The off-time of M
PFC
is determined by the time it takes the
L
PFC
current to discharge to zero. This zero current level
is detected by a secondary winding on L
PFC
which is
connected to the ZX pin. A positive-going edge
exceeding the internal 2 V threshold (V
ZXTH+
) signals the
beginning of the off-time. A negative-going edge on the
ZX pin falling below (V
ZXTH+
- V
ZXHYS
) will occur when the
L
PFC
current discharges to zero which signals the end of
the off-time and M
is turned on again (Fig. 10). The
cycle repeats itself indefinitely until the PFC section is
disabled due to a fault detected by the ballast section
(fault mode), an over-voltage or undervoltage condition
on the DC bus, or, the negative transition of ZX pin
voltage does not occur. Should the negative edge on the
ZX pin not occur, M
will remain off until the watch-dog
timer forces a turn-on of M
PFC
for an on-time duration
programmed by the voltage on the COMP pin. The
watch-dog pulses occur every 400 μs (t
WD
) indefinitely
until a correct positive- and negative-going signal is
detected on the ZX pin and normal PFC operation is
resumed.
0
0
0
I
LPFC
PFC
pin
ZX
pin
Fig. 10:
LPFC current, PFC pin and ZX pin timing
diagram
A fixed on-time of M
PFC
over an entire cycle of the line
input voltage produces a peak inductor current which
naturally follows the sinusoidal shape of the line input
voltage. The smoothed averaged line input current is in
phase with the line input voltage for high power factor but
the total harmonic distortion (THD), as well as the
individual higher harmonics, of the current can still be too
high. This is mostly due to cross-over distortion of the
line current near the zero-crossings of the line input
voltage. To achieve low harmonics which are acceptable
to international standard organizations and general
market requirements, an additional on-time modulation
circuit has been added to the PFC control. This circuit
dynamically increases the on-time of M
PFC
as the line
input voltage nears the zero-crossings (Fig. 11). This
causes the peak L
PFC
current, and therefore the smoothed
line input current, to increase slightly higher near the
zero-crossings of the line input voltage. This reduces the
amount of cross-over distortion in the line input current
which reduces the THD and higher harmonics to low
levels.
Over-Voltage Protection (OVP)
Should over-voltage occur on the DC bus causing the
VBUS pin to exceed the internal 4.3 V threshold (V
BUSOV+
),
the PFC output is disabled (set to a logic ‘low’). When the
DC bus decreases again causing the VBUS pin to
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