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參數(shù)資料
| 型號： | IPM6220ACAZA-T |
| 廠商： | INTERSIL CORP |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | Circular Connector; No. of Contacts:4; Series:; Body Material:Aluminum Alloy; Connecting Termination:Solder; Connector Shell Size:22; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:22-4 RoHS Compliant: No |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PDSO24 |
| 封裝： | 0.150 INCH, LEAD FREE, PLASTIC, SSOP-24 |
| 文件頁數(shù)： | 9/14頁 |
| 文件大小： | 358K |
| 代理商： | IPM6220ACAZA-T |
9
3.3V Main and 5V Main Soft Start, Sequencing and
Stand-by
See Table 1 for the output voltage control algorithm. The 5V
Main and 3.3V Main converters are enabled if SDWN1 and
SDWN2 are high and SDWNALL is also high. The stand-by
mode is defined as a condition when SDWN1 and SDWN2 are
low and the PWM converters are disabled but SDWNALL is
high (3.3V ALWAYS and 5V ALWAYS outputs are enabled). In
this power saving mode, only the low power micro-controller
and keyboard may be powered.
Soft start of the 3.3V Main and 5V Main converters is
accomplished by means of capacitors connected from pins
SDWN1 and SDWN2 to ground. In conjunction with 5
μ
A
internal current sources, they provide a controlled rise of the
3.3V Main and 5V Main output voltages. The value of the
soft-start capacitors can be calculated from the following
expression.
Where Tss
is the desired soft-start time.
By varying the values of the soft-start capacitors, it is possible
to provide sequencing of the main outputs at start-up.
Figure 7 shows the soft-start initiated by the SDWNALL pin
being pulled high with the Vbatt input at 10.8V and the
resulting 3.3V Main and 5V Main outputs.
While the SDWNALL pin is held low, prior to T0, all outputs
are off. Pulling SDWNALL high enables the 3.3V ALWAYS
and 5V ALWAYS outputs. With the 3.3V Main and 5V Main
outputs enabled, at T1, the internal 5
μ
A current sources start
charging the soft start capacitors on the SDWN1 and
SDWN2 pins. At T2 the outputs begin to rise and because
they both have the same value of soft-start capacitors,
0.022
μ
F, they both reach regulation at the same time, T3.
The soft-start capacitors continue to charge and are
completely charged at T4.
12V Converter Architecture
The 12V boost converter generates its output voltage from
the 5V Main output. An external MOSFET, inductor, diode
and capacitor are required to complete the circuit. The
output signal is fed back to the controller via an external
resistive divider. The boost controller can be disabled by
connecting the VSEN3 pin to 5V ALWAYS.
The control circuit for the 12V converter consists of a 3:1
frequency divider which drives a ramp generator and resets
a PWM latch as shown in Figure 8. The width of the CLK/3
pulses is equal to the period of the main clock, limiting the
duty cycle to 33%. The output of a non-inverting error
amplifier is compared with the rising ramp voltage. When the
ramp voltage becomes higher than the error signal, the
PWM comparator sets the latch and the output of the gate
driver is pulled high providing leading edge, voltage mode
PWM. The falling edge of the CLK/3 pulses resets the latch
and pulls the output of the gate driver low.
The 33% maximum duty cycle of the converter guarantees
discontinuous inductor current and unconditional stability
over all operating conditions.
The boost converter with the limited duty cycle and
discontinuous inductor current can deliver to the load a
limited amount of power before the output voltage starts to
drop. When the duty cycle has reached DMAX, the control
TABLE 1. OUTPUT VOLTAGE CONTROL
SDWNALL SDWN1
SDWN2
3V AND 5V
ALWAYS
5V MAIN 3V MAIN
0
X
X
OFF
OFF
OFF
1
0
0
ON
OFF
OFF
1
1
0
ON
ON
OFF
1
0
1
ON
OFF
ON
1
1
1
ON
ON
ON
Css
----------------------------
=
SDWN2, 2V/DIV.
3.3V
OUT
, 2V/DIV.
5V
OUT
, 2V/DIV.
0V
0V
4ms/DIV.
SDWN1, 2V/DIV.
T0 T1
T2
T3
T4
SDWNALL,10V/DIV
.
V
IN
= 10.8V
FIGURE 7. SOFT START ON 3.3V AND 5V OUTPUTS
-
EA3
REF
+
Q
Q
R
S
PWM
LATCH 3
VSEN3
+
CLK
DIVIDER
3:1
RAMP
GENERATOR
CLK/3
CLK/3
GATE3
RAMP
t
t
t
t
CLK
CLK/3
RAMP
VEA3
GATE3
PWM
COMPARATOR
FIGURE 8. 12V BOOST OPERATION
IPM6220
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IPM6220ACAZ-T | Advanced Triple PWM and Dual Linear Power Controller for Portable Applications |
| IPM6220EVAL1 | Advanced Triple PWM and Dual Linear Power Controller for Portable Applications |
| IPM6220ACA | Advanced Triple PWM and Dual Linear Power Controller for Portable Applications |
| IPM6220ACAZ | Advanced Triple PWM and Dual Linear Power Controller for Portable Applications |
| IPM6220CA | Advanced Triple PWM and Dual Linear Power Controller for Portable |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IPM6220ACAZ-T | 功能描述:電流型 PWM 控制器 30V CS80 FSC PROCESS W/IMPROVED ESD STRUC RoHS:否 制造商:Texas Instruments 開關(guān)頻率:27 KHz 上升時間: 下降時間: 工作電源電壓:6 V to 15 V 工作電源電流:1.5 mA 輸出端數(shù)量:1 最大工作溫度:+ 105 C 安裝風格:SMD/SMT 封裝 / 箱體:TSSOP-14 |
| IPM6220CA | 制造商:Rochester Electronics LLC 功能描述:MULTI-OUTPUT SYSTEM ELECTRONICS REGULATOR FOR MOBIL PCS - Bulk |
| IPM6220CB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| IPM6220EVAL1 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Advanced Triple PWM Only Mode and Dual Linear Power Controller for Portable Applications |
| IPM-C112 | 制造商:JDSU 制造商全稱:JDS Uniphase Corporation 功能描述:Miniature Integrated Power Monitor |
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