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參數(shù)資料
| 型號(hào)： | IP82C84A |
| 廠商： | INTERSIL CORP |
| 元件分類： | XO, clock |
| 英文描述： | CMOS Clock Generator Driver |
| 中文描述： | 8 MHz, PROC SPECIFIC CLOCK GENERATOR, PDIP18 |
| 封裝： | PLASTIC, DIP-18 |
| 文件頁數(shù)： | 8/10頁 |
| 文件大?。?/td> | 89K |
| 代理商： | IP82C84A |
4-294
AC Testing Input, Output Waveform
Test Load Circuits
NOTES:
1. C
L
=100pF for CLK output.
2. C
L
= 50pF for all outputs except CLK.
3. C
L
= Includes probe and jig capacitance.
FIGURE 5. TEST LOAD MEASUREMENT CONDITIONS
FIGURE 6. TCHCL, TCLCH LOAD CIRCUITS
FIGURE 7. TRYLCL, TRYHCH LOAD CIRCUITS
C
L
(SEE NOTE 3)
OUTPUT FROM
DEVICE UNDER TEST
R = 740
FOR ALL OUTPUTS
EXCEPT CLK
463
FOR CLK OUTPUT
2.25V
C1
C2
X1
X2
CSYNC
CLK
LOAD
(SEE NOTE 1)
F/C
EF1
CSYNC
CLK
LOAD
(SEE NOTE 1)
F/C
V
CC
PULSE
GENERATOR
C1
C2
X1
X2
CLK
LOAD
(SEE NOTE 1)
LOAD
(SEE NOTE 2)
CSYNC
F/C
AEN2
PULSE
GENERATOR
TRIGGER
V
CC
24MHz
READY
OSC
AEN1
RDY2
EF1
CLK
LOAD
(SEE NOTE 1)
F/C
V
CC
PULSE
GENERATOR
CSYNC
RDY2
AEN2
LOAD
(SEE NOTE 2)
AEN1
READY
TRIGGER
PULSE
GENERATOR
1.5V
1.5V
V
OL
V
IL
- 0.4V
INPUT
V
IH
+ 0.4V
OUTPUT
V
OH
NOTE: Input test signals must switch between V
IL
(maximum) -0.4V and V
IH
(minimum) +0.4V. RES and F/C must switch between 0.4V and
V
CC
-0.4V. Input rise and fall times driven at 1ns/V. V
IL
≤
V
IL
(max) -0.4V for CSYNC pin. V
CC
-4.5V and 5.5V.
82C84A
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