參數(shù)資料
型號： IP80C88-2
廠商： Intersil
文件頁數(shù)： 15/38頁
文件大?。?/td> 0K
描述： IC CPU 8/16BIT 5V 8MHZ 40-DIP
標(biāo)準(zhǔn)包裝： 99
處理器類型： 80C88 8/16-位
速度： 8MHz
電壓： 4.75 V ~ 5.25 V
安裝類型： 通孔
封裝/外殼： 40-DIP（0.600"，15.24mm）
供應(yīng)商設(shè)備封裝： 40-DIP
包裝： 管件
22
FN2949.4
February 22, 2008
(32)
TCLMCL
MCE Inactive Delay (Note
CL = 100pF
for all 80C88 outputs in
addition
to
internal
loads.
-15
ns
(33)
TCLDV
Data Valid Delay
10
110
10
60
ns
(34)
TCLDX2
Data Hold Time
10
-
10
-
ns
(35)
TCVNV
Control Active Delay (Note
545
ns
(36)
TCVNX
Control Inactive Delay (Note
10
45
10
45
ns
(37)
TAZRL
Address Float to Read Active
0-
ns
(38)
TCLRL
RD Active Delay
10
165
10
100
ns
(39)
TCLRH
RD Inactive Delay
10
150
10
80
ns
(40)
TRHAV
RD Inactive to Next Address Active
TCLCL
- 45
-
TCLCL
- 40
-ns
(41)
TCHDTL
Direction Control Active Delay
(Note
-50
ns
(42)
TCHDTH
Direction Control Inactive Delay
(Note 1)
-30
ns
(43)
TCLGL
GT Active Delay
085
050
ns
(44)
TCLGH
GT Inactive Delay
085
050
ns
(45)
TRLRH
RD Width
2TCLCL
- 75
-
2TCLCL
- 50
-ns
(46)
TOLOH
Output Rise Time
From 0.8V to 2.0V
-15
ns
(47)
TOHOL
Output Fall Time
From 2.0V to 0.8V
-15
ns
NOTES:
3. Signal at 82C84A or 82C88 shown for reference only.
4. Setup requirement for asynchronous signal only to guarantee recognition at next CLK.
5. Applies only to T2 state (8ns into T3).
6. The 80C88 actively pulls the RQ/GT pin to a logic one on the following clock low time.
7. Status lines return to their inactive (logic one) state after CLK goes low and READY goes high.
AC Electrical Specifications
VCC = 5.0V±10%; TA = 0°C to +70°C (C80C88, C80C88-2)
VCC = 5.0V±10%; TA = -40°C to +85°C (I80C88, I80C88-2)
VCC = 5.0V±10%; TA = -55°C to +125°C (M80C88)
MAX MODE SYSTEM (USING 82C88 BUS CONTROLLER) (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
80C88
80C88-2
UNITS
MIN
MAX
MIN
MAX
80C88
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