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參數(shù)資料
| 型號： | IP178CHLF |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 8 Port 10/100 Ethernet Integrated Switch |
| 中文描述： | 8端口10/100以太網(wǎng)集成開關(guān) |
| 文件頁數(shù)： | 48/91頁 |
| 文件大?。?/td> | 1244K |
| 代理商： | IP178CHLF |
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IP178C
Preliminary Data Sheet
Copyright
2004, IC Plus Corp.
48/91
October 27, 2005
IP178C-DS-R09
PHY
MII status register (address 01)
0
1.15
MII
ROM
R/W
Description
Default
--
RO
100Base-T4 capable
1 = 100Base-T4 capable
0 = not 100Base-T4 capable
IP178C does not support 100Base-T4. This bit is fixed to be 0.
100Base-X full duplex Capable
1 = 100Base-X full duplex capable
0 = not 100Base-X full duplex capable
The default of this bit will change depend on the external
setting of IP178C. If external pin setting without 100Base-X
full duplex support, then this bit will change default to logic 0.
100Base-X half duplex Capable
1 = 100Base-X half duplex capable
0 = not 100Base-X half duplex capable
The default of this bit will change depend on the external
setting of IP178C. If external pin setting without 100Base-X
half duplex support, then this bit will change default to logic 0
10Base-T full duplex Capable
1 = 10Base-T full duplex capable
0 = not 10Base-T full duplex capable
The default of this bit will change depend on the external
setting of IP178C. If external pin setting without 100Base-T
full duplex support, then this bit will change default to logic 0
10Base-T half duplex Capable
1 = 10Base-T half duplex capable
0 = not 10Base-T half duplex capable
The default of this bit will change depend on the external
setting of IP178C. If external pin setting without 100Base-X
full duplex support, then this bit will change default to logic 0
Reserved
Ignore on read
MF preamble Suppression
1 = preamble may be suppressed
0 = preamble always required
Auto-Negotiation Complete
1 = Auto-Negotiation complete
0 = Auto-Negotiation in progress
When read as logic 1, indicates that the Auto-Negotiation
process has been completed, and the contents of register 4
and 5 are valid. When read as logic 0, indicates that the
Auto-Negotiation process has not been completed, and the
contents of register 4 and 5 are meaningless. If
Auto-Negotiation is disabled (bit 0.12 set to logic 0), then this
bit will always read as logic 0.
0
0
1.14
--
RO
1
0
1.13
--
RO
1
0
1.12
--
RO
1
0
1.11
--
RO
1
0
1[10:7]
--
RO
-
0
1.6
--
RO
1
0
1.5
--
RO
0
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