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參數(shù)資料
| 型號(hào)： | IMISC661BAB |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | PROC SPECIFIC CLOCK GENERATOR, PQFP52 |
| 文件頁(yè)數(shù)： | 2/5頁(yè) |
| 文件大?。?/td> | 287K |
| 代理商： | IMISC661BAB |
SC661
Clock Generator for 3 DIMM, USB and 2.5V Pentium
Design
Approved Product
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
Rev.1.7
5/19/98
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Page 2 of 5
PIN DESCRIPTION
Xin, Xout - These pins form an on-chip reference
oscillator when connected to terminals of an external
parallel resonant crystal (nominally 14.318 MHz).
Xin
may also serve as input for an externally generated
reference signal in which case Xout must be kept
unconnected.
S0, S1, and S2 - Standard frequency select inputs.
These inputs have internal pull-ups(> 100K
).
CPU(1:4) - Low skew (<250 pS) clock outputs for host
frequencies such as CPU, Chipset, Cache, etc... CPU1-
CPU4 voltage level is controlled by VDDCPU.
SDRM(1:12) - Low skew (<250 pS) clock outputs for
SDRAM. Voltage level is controlled by VDDRM.
IOAPIC - Buffered output clock of the crystal. Voltage
level is controlled by VDDIO.
PCI(1:8) - Low skew (<250pS) clock outputs for PCI
frequencies.
These buffers voltage level is controlled
by VDD.
REF - Buffered output of on-chip reference.
48MHz - Frequency output for USB.
24MHz - Frequency output for Floppy Drive.
VSS - Circuit ground.
VDD - Positive power supply.
VDDCPU - 3.3V/2.5V logic level control for CPU(1:4)
outputs. Voltage cannot be greater than VDD.
VDDRM - 3.3V logic level control for SDRM(1:12)
outputs. Voltage cannot be greater than VDD.
VDDIO - 3.3V/2.5V logic level control for IOAPIC output.
Voltage cannot be greater than VDD.
MAXIMUM RATINGS
Voltage Relative to VSS:
-0.3V
Voltage Relative to VDD:
0.3V
Storage Temperature:
0C to + 125C
Operating Temperature:
0C to +70C
Maximum Power Supply:
7V
This device contains circuitry to protect the inputs
against damage due to high static voltages or electric
field; however, precautions should be taken to avoid
application of any voltage higher than the maximum
rated voltages to this circuit. For proper operation, Vin
and Vout should be constrained to the range:
VSS<(Vin or Vout)<VDD
Unused inputs must always be tied to an appropriate
logic voltage level (either VSS or VDD).
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