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參數(shù)資料
| 型號(hào)： | IMIB9688AYB |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | LOW SKEW CLOCK DRIVER, PDSO48 |
| 文件頁數(shù)： | 5/8頁 |
| 文件大?。?/td> | 75K |
| 代理商： | IMIB9688AYB |
B9688
I
2C System Clock Buffer
Preliminary
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
Rev.1.2
6/23/1999
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Page 5 of 8
DC Parameters
Characteristic
Symbol
Min
Typ
Max
Units
Conditions
Input Low Voltage (OE)
VIL
-
0.8
Vdc
-
Input High Voltage (OE)
VIH
2.0
-
Vdc
-
Input Low Current
IIL
-66
-
A
Input High Current
IIH
66
A
Input Low Voltage (I
2C)
VILisc
-
1.0
Vdc
Input High Voltage (I
2C)
VIHisc
2.2
-
Vdc
Tri-State leakage Current
Ioz
-
10
A
Dynamic Supply Current
Idd66
9
-
160
mA
Input frequency = 66 MHz - All outputs
on and at 30 pF load
Dynamic Supply Current
Idd100
12
-
220
mA
Input frequency 100 MHz - All outputs on
and at 30 pF load
Static Supply Current
Isdd
-
4
mA
All outputs disabled no input clock
Input pin capacitance
Cin
-
5
pF
Pin Inductance
Lpin
-
7
nH
Output Capacitance
Cout
-
6
pF
VDD = 3.3V
±5%, , TA = 0C to +70C
AC Parameters
Characteristic
Symbol
Min
Typ
Max
Units
Conditions
Output Duty Cycle
-
45
50
55
%
Measured at 1.5V (50/50 in)
Buffer out/out Skew All
Buffer Outputs
tSKEW
-
250
pS
35 pF Load Measured at 1.5V
Buffer input to output Skew
tDLY
2.0
0
5.0
nS
Jitter Cycle to Cycle*
TJCC
100
pS
@ 30 pF loading
Jitter Absolute (Peak to
Peak)*
TJabs
150
pS
@ 30 pF loading
VDD = 3.3V
±5%, , TA = 0C to +70C
*This jitter is additive to the input clock’s jitter.
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