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107
8183F–AVR–06/12
ATtiny24A/44A/84A
Table 12-2 shows COM1x[1:0] bit functionality when WGM1[3:0] bits are set to a Normal or a
CTC mode (non-PWM).
Table 12-3 shows COM1x[1:0] bit functionality when WGM1[3:0] bits are set to fast PWM mode.
Note:
1. A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. In
this case the compare match is ignored, but the set or clear is done at BOTTOM. See
“FastTable 12-4 shows COM1x[1:0] bit functionality when WGM1[3:0] bits are set to phase correct or
phase and frequency correct PWM mode.
Note:
1. A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set.
Table 12-2.
Compare Output Mode, non-PWM
COM1A1
COM1B1
COM1A0
COM1B0
Description
0
Normal port operation, OC1A/OC1B disconnected
0
1
Toggle OC1A/OC1B on Compare Match
10
Clear OC1A/OC1B on Compare Match
(Set output to low level)
11
Set OC1A/OC1B on Compare Match
(Set output to high level).
Table 12-3.
Compare Output Mode, Fast
PWMCOM1A1
COM1B1
COM1A0
COM1B0
Description
0
Normal port operation, OC1A/OC1B disconnected
01
WGM13=0: Normal port operation, OC1A/OC1B disconnected
WGM13=1: Toggle OC1A on Compare Match, OC1B reserved
10
Clear OC1A/OC1B on Compare Match, set OC1A/OC1B at
BOTTOM (non-inverting mode)
11
Set OC1A/OC1B on Compare Match, clear OC1A/OC1B at
BOTTOM (inverting mode)
Table 12-4.
Compare Output Mode, Phase Correct and Phase & Frequency Correct
PWMCOM1A1
COM1B1
COM1A0
COM1B0
Description
0
Normal port operation, OC1A/OC1B disconnected
01
WGM13=0: Normal port operation, OC1A/OC1B disconnected
WGM13=1: Toggle OC1A on Compare Match, OC1B reserved
10
Clear OC1A/OC1B on Compare Match when up-counting
Set OC1A/OC1B on Compare Match when downcounting
11
Set OC1A/OC1B on Compare Match when up-counting
Clear OC1A/OC1B on Compare Match when downcounting