參數(shù)資料
型號： IDT89HPES32T8ZHBXG
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 33/37頁
文件大?。?/td> 0K
描述： IC PCI SW 32LANE 8PORT 500-SBGA
標準包裝： 27
系列： PRECISE™
類型： PCI Express 開關(guān) - Gen1
應(yīng)用： 服務(wù)器，儲存，通信，嵌入式，消費品
安裝類型： 表面貼裝
封裝/外殼： 500-LBGA
供應(yīng)商設(shè)備封裝： 500-SBGA（31x31）
包裝： 托盤
其它名稱： 89HPES32T8ZHBXG
5 of 37
March 25, 2008
IDT 89PES32T8 Data Sheet
Pin Description
The following tables lists the functions of the pins provided on the PES32T8. Some of the functions listed may be multiplexed onto the same pin.
The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low)
level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level.
Signal
Type
Name/Description
PE0RP[3:0]
PE0RN[3:0]
I
PCI Express Port 0 Serial Data Receive. Differential PCI Express receive
pairs for port 0. Port 0 is the upstream port.
PE0TP[3:0]
PE0TN[3:0]
O
PCI Express Port 0 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 0. Port 0 is the upstream port.
PE1RP[3:0]
PE1RN[3:0]
I
PCI Express Port 1 Serial Data Receive. Differential PCI Express receive
pairs for port 1. When port 0 is merged with port 1, these signals become
port 0 receive pairs for lanes 4 through 7.
PE1TP[3:0]
PE1TN[3:0]
O
PCI Express Port 1 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 1. When port 0 is merged with port 1, these signals
become port 0 transmit pairs for lanes 4 through 7.
PE2RP[3:0]
PE2RN[3:0]
I
PCI Express Port 2 Serial Data Receive. Differential PCI Express receive
pairs for port 2.
PE2TP[3:0]
PE2TN[3:0]
O
PCI Express Port 2 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 2.
PE3RP[3:0]
PE3RN[3:0]
I
PCI Express Port 3 Serial Data Receive. Differential PCI Express receive
pairs for port 3. When port 2 is merged with port 3, these signals become
port 2 receive pairs for lanes 4 through 7.
PE3TP[3:0]
PE3TN[3:0]
O
PCI Express Port 3 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 3. When port 2 is merged with port 3, these signals
become port 2 transmit pairs for lanes 4 through 7.
PE4RP[3:0]
PE4RN[3:0]
I
PCI Express Port 4 Serial Data Receive. Differential PCI Express receive
pairs for port 4.
PE4TP[3:0]
PE4TN[3:0]
O
PCI Express Port 4 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 4.
PE5RP[3:0]
PE5RN[3:0]
I
PCI Express Port 5 Serial Data Receive. Differential PCI Express receive
pairs for port 5. When port 4 is merged with port 5, these signals become
port 4 receive pairs for lanes 4 through 7.
PE5TP[3:0]
PE5TN[3:0]
O
PCI Express Port 5 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 5. When port 4 is merged with port 5, these signals
become port 4 transmit pairs for lanes 4 through 7.
PE6RP[3:0]
PE6RN[3:0]
I
PCI Express Port 6 Serial Data Receive. Differential PCI Express receive
pairs for port 6.
PE6TP[3:0]
PE6TN[3:0]
O
PCI Express Port 6 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 6.
PE7RP[3:0]
PE7RN[3:0]
I
PCI Express Port 7 Serial Data Receive. Differential PCI Express receive
pairs for port 7. When port 6 is merged with port 7, these signals become
port 6 receive pairs for lanes 4 through 7.
Table 2 PCI Express Interface Pins (Part 1 of 2)
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