Figure - 9 Power-Up Reset Circuit 2.11 POWER" />
參數(shù)資料
型號(hào)： IDT82V3012PVG8
廠商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 8/32頁(yè)
文件大?。?/td> 0K
描述： IC PLL WAN T1/E1/OC3 DUAL 56SSOP
標(biāo)準(zhǔn)包裝： 1,000
類(lèi)型： 時(shí)鐘/頻率發(fā)生器，多路復(fù)用器
PLL： 是
主要目的： 以太網(wǎng)，SONET/SDH，Stratum，T1/E1/OC3
輸入： 時(shí)鐘
輸出： CMOS，LVDS，TTL
電路數(shù)： 1
比率 - 輸入:輸出： 2:12
差分 - 輸入:輸出： 無(wú)/是
頻率 - 最大： 32.768MHz
電源電壓： 3 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 56-BSSOP（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 56-SSOP
包裝： 帶卷 (TR)
其它名稱(chēng)： 82V3012PVG8
Functional Description
16
February 6, 2009
IDT82V3012
T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS
Figure - 9 Power-Up Reset Circuit
2.11
POWER SUPPLY FILTERING TECHNIQUES
To achieve optimum jitter performance, power supply filtering is
required to minimize supply noise modulation of the output clocks. The
common sources of power supply noise are switching power supplies
and the high switching noise from the outputs to the internal PLL. The
82V3012 provides separate power pins: VDDA and VDDD. VDDA pins are
for the internal analog PLL, and VDDD pins are for the core logic as well
as I/O driver circuits.
To minimize switching power supply noise generated by the
switching regulator, the power supply output should be filtered with
sufficient bulk capacity to minimize ripple and 0.1 uF (0402 case size,
ceramic) capacitors to filter out the switching transients.
For the 82V3012, the decoupling for VDDA and VDDD are handled
individually. VDDD and VDDA should be individually connected to the
power supply plane through vias, and bypass capacitors should be used
for each pin. Figure - 10 illustrates how bypass capacitor and ferrite
bead should be connected to each power pin.
The analog power supply VDDA should have low impedance. This
can be achieved by using one 10 uF (1210 case size, ceramic) and at
least two 0.1 uF (0402 case size, ceramic) capacitors in parallel. The 0.1
uF (0402 case size, ceramic) capacitors must be placed next to the
VDDA pins and as close as possible. Note that the 10 uF capacitor must
be of 1210 case size, and it must be ceramic for lowest possible ESR
(Effective Series Resistance). The 0.1 uF should be of case size 0402,
which offers the lowest ESL (Effective Series Inductance) to achieve low
impedance towards the high speed range.
For VDDD, at least three 0.1 uF (0402 case size, ceramic) and one 10
uF (1210 case size, ceramic) capacitors are recommended. The 0.1 uF
capacitors should be placed as close to the VDDD pins as possible.
Please refer to evaluation board schematic for details.
Figure - 10 IDT82V3012 Power Decoupling Scheme
3.3 V
R
10 k
Rp
1 k
C
1
F
RST
IDT82V3012
SLF7028T-100M1R1
10
F
0.1
F
0.1
F
37
48
3.3 V
SLF7028T-100M1R1
10
F
0.1
F
0.1
F
13
19
0.1
F
26
3.3 V
IDT82V3012
V
DDA
V
DDA
V
DDD
V
DDD
V
DDD
V
SS
V
SS
V
SS
V
SS
V
SS
12
18
27
38
47
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參數(shù)描述
IDT82V3155 制造商:IDT 制造商全稱(chēng):Integrated Device Technology 功能描述:ENHANCED T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS
IDT82V3155PV 制造商:IDT 制造商全稱(chēng):Integrated Device Technology 功能描述:ENHANCED T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS
IDT82V3155PVG 功能描述:IC PLL WAN T1/E1/OC3 DUAL 56SSOP RoHS:是 類(lèi)別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專(zhuān)用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類(lèi)型:時(shí)鐘緩沖器/驅(qū)動(dòng)器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱(chēng):93786AFT
IDT82V3155PVG8 功能描述:IC PLL WAN T1/E1/OC3 DUAL 56SSOP RoHS:是 類(lèi)別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專(zhuān)用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類(lèi)型:時(shí)鐘緩沖器/驅(qū)動(dòng)器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱(chēng):93786AFT
IDT82V3202 制造商:IDT 制造商全稱(chēng):Integrated Device Technology 功能描述:EBU WAN PLL
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