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參數(shù)資料
| 型號： | IDT82V2048SDAG |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 7/62頁 |
| 文件大小： | 0K |
| 描述： | IC LIU T1/E1 8CH SHORT 144-TQFP |
| 標(biāo)準(zhǔn)包裝： | 5,000 |
| 類型： | 線路接口裝置（LIU） |
| 規(guī)程： | E1 |
| 電源電壓： | 3.13 V ~ 3.47 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 144-LQFP |
| 供應(yīng)商設(shè)備封裝： | 144-TQFP（20x20） |
| 包裝： | 托盤 |
| 其它名稱： | 82V2048SDAG |
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15
IDT82V2048S OCTAL T1/E1 SHORT HAUL LIU WITH SINGLE ENDED OPTION
INDUSTRIAL TEMPERATURE RANGES
2.3
CLOCK EDGES
The active edge of RCLKn and SCLK are selectable. If pin CLKE is
high, the active edge of RCLKn is the rising edge, as for SCLK, that is
falling edge. On the contrary, if CLKE is low, the active edge of RCLK is
the falling edge and that of SCLK is rising edge. Pins RDn/RDPn, CVn/
RDNn and SDO are always active high, and those output signals are
clocked out on the active edge of RCLKn and SCLK respectively. See
However, in dual rail mode without clock recovery, pin CLKE is used to
set the active level for RDPn/RDNn raw slicing output: High for active
high polarity and low for active low. It should be noted that data on pin
SDI are always active high and are sampled on the rising edges of
SCLK. The data on pin TDn/TDPn or BPVIn/TDNn are also always
active high but are sampled on the falling edges of TCLKn, despite the
level on CLKE.
2.4
RECEIVER
In receive path with differential termination, the line signals couple
into RRINGn and RTIPn via a transformer and are converted into RZ
digital pulses by a data slicer. In the receive path with Single Ended
termination (E1 75
), the line signal is coupled into RTIPn via a trans-
former and is converted into RZ digital pulses by a data slicer. Adapta-
tion for attenuation is achieved using an integral peak detector that sets
the slicing levels. Clock and data are recovered from the received RZ
digital pulses by a digital phase-locked loop that provides jitter accom-
modation. After passing through the selectable jitter attenuator, the
recovered data are decoded using B8ZS/HDB3 or AMI line code rules
and clocked out of pin RDn in single rail mode, or presented on RDPn/
RDNn in an undecoded dual rail NRZ format. Loss of signal, alarm indi-
cation signal, line code violation and excessive zeros are detected. The
presence of programmable inband loopback codes are also detected.
These various changes in status may be enabled to generate interrupts.
2.4.1
SINGLE ENDED RECEIVE TERMINATION
The 82V2048S offers a Single Ended receive termination mode to
enable a true single ended termination on both the primary and
secondary side of the transformer. Refer to Figure-13 for details. Single
Ended receive termination is only available when the device is operated
in Host mode. To enable the Single Ended receive termination, bit SRX
in register e-SRX has to be set to ‘1’ which will configure the corre-
sponding receiver in Single Ended receive termination mode.
2.4.2
PEAK DETECTOR AND SLICER
The slicer determines the presence and polarity of the received
pulses. In data recovery mode, the raw positive slicer output appears on
RDPn while the negative slicer output appears on RDNn. In clock and
data recovery mode, the slicer output is sent to Clock and Data
Recovery circuit for abstracting retimed data and optional decoding. The
slicer circuit has a built-in peak detector from which the slicing threshold
is derived. The slicing threshold is default to 50% (typical) of the peak
value.
Signals with an attenuation of up to 11 dB (from 2.4 V) can be recov-
ered by the receiver. To provide immunity from impulsive noise, the peak
detectors are held above a minimum level of 0.1 V typically, despite the
received signal level.
2.4.3
CLOCK AND DATA RECOVERY
The Clock and Data Recovery is accomplished by Digital Phase
Locked Loop (DPLL). The DPLL is clocked 16 times of the received
clock rate, i.e. 24.704 MHz in T1 mode or 32.768 MHz in E1 mode. The
recovered data and clock from DPLL is then sent to the selectable Jitter
Attenuator or decoder for further processing.
The clock recovery and data recovery mode can be selected on a per
channel basis by setting bit CRSn in register e-CRS. When bit CRSn is
defaulted to ‘0’, the corresponding channel operates in data and clock
recovery mode. The recovered clock is output on pin RCLKn and re-
timed NRZ data are output on pin RDPn/RDNn in dual rail mode or on
RDn in single rail mode. When bit CRSn is set to ‘1’, dual rail mode with
data recovery is enabled in the corresponding channel and the clock
recovery is bypassed. In this condition, the analog line signals are
converted to RZ digital bit streams on the RDPn/RDNn pins and inter-
nally connected to an EXOR which is fed to the RCLKn output for
external clock recovery applications.
If MCLK is pulled high, all the receivers will enter the dual rail mode
with data recovery. In this case, register e-CRS is ignored.
2.4.4
B8ZS/HDB3/AMI LINE CODE RULE
Selectable B8ZS/HDB3 and AMI line coding/decoding is provided
when the device is configured in single rail mode. B8ZS rules for T1 and
HDB3 rules for E1 are enabled by setting bit CODE in register GCF to ‘0’
or pulling pin CODE low. AMI rule is enabled by setting bit CODE in
register GCF to ‘1’ or pulling pin CODE high. The settings affect all eight
channels.
Individual line code rule selection for each channel, if needed, is
available by setting bit SINGn in register e-SING to ‘1’ (to activate bit
CODEn in register e-CODE) and programming bit CODEn to select line
code rules in the corresponding channel: ‘0’ for B8ZS/HDB3, while ‘1’ for
AMI. In this case, the value in bit CODE in register GCF or pin CODE for
global control is unaffected in the corresponding channel and only affect
in other channels.
In dual rail mode, the decoder/encoder are bypassed. Bit CODE in
register GCF, bit CODEn in register e-CODE and pin CODE are ignored.
The configuration of the line code rule is summarized in Table-5.
2.4.5
LOSS OF SIGNAL (LOS) DETECTION
The Loss of Signal Detector monitors the amplitude and density of
the received signal on receiver line before the transformer (measured on
reported by pulling pin LOSn high. At the same time, LOS alarm regis-
ters track LOS condition. When LOS is detected or cleared, an interrupt
will generate if not masked. In host mode, the detection supports the
ANSI T1.231 for T1 mode, ITU G.775 and ETSI 300 233 for E1 mode. In
hardware mode, it supports the ITU G.775 and ANSI T1.231.
Table-6 summarizes the conditions of LOS in clock recovery mode.
During LOS, the RDPn/RDNn continue to output the sliced data
when bit AISE in register GCF is set to ‘0’ or output all ones as AIS
(alarm indication signal) when bit AISE is set to ‘1’. The RCLKn is
replaced by MCLK only if the bit AISE is set.
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