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參數(shù)資料
| 型號： | IDT82V2048EDR |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 26/76頁 |
| 文件大小： | 0K |
| 描述： | IC LIU T1/E1 8CH SHORT 208-TQFP |
| 標準包裝： | 12 |
| 類型： | 線路接口裝置（LIU） |
| 規(guī)程： | E1 |
| 電源電壓： | 3.13 V ~ 3.47 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 208-BFQFP |
| 供應(yīng)商設(shè)備封裝： | 208-PQFP（28x28） |
| 包裝： | 托盤 |
| 其它名稱： | 82V2048EDR |
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32
INDUSTRIAL
TEMPERATURE RANGES
OCTAL CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
3.10 MCLK AND TCLK
3.10.1 MASTER CLOCK (MCLK)
MCLK is an independent, free-running reference clock. MCLK is 1.544
MHz or 37.056 MHz for T1/J1 applications and 2.048 MHz or 49.152 MHz
in E1 mode. This reference clock is used to generate several internal ref-
erence signals:
Timing reference for the integrated clock recovery unit.
Timing reference for the integrated digital jitter attenuator.
Timing reference for microcontroller interface.
Generation of RCLK signal during a loss of signal condition if AIS is
enabled.
Reference clock during a blue alarm Transmit All Ones (TAOS), all
zeros, PRBS/QRSS and inband loopback patterns if it is selected
as the reference clock. For ATAO and AIS, MCLK is always used as
the reference clock.
Figure-20 shows the chip operation status in different conditions of
MCLK and TCLKn. The missing of MCLK will set all the eight TTIP/TRING
to high impedance state.
3.10.2 TRANSMIT CLOCK (TCLK)
The TCLKn is used to sample the transmit data on TDn/TDPn, TDNn.
The active edge of TCLKn can be selected by the TCLK_SEL bit (TCF0,
02H...). During Transmit All Ones, PRBS/QRSS patterns or Inband Loop-
back Code,either TCLKnor MCLK can beused as the referenceclock. This
is selected by the PATT_CLK bit (MAINT0, 0AH...).
But for Automatic Transmit All Ones and AIS, only MCLK is used as the
reference clock and the PATT_CLK bit is ignored. In Automatic Transmit
All Ones condition, the ATAO bit (MAINT0, 0AH) is set to ‘1’. In AIS condi-
tion, the AISE bit (MAINT0, 0AH) is set to ‘1’.
If TCLKn has been missing for more than 70 MCLK cycles, TCLK_LOS
bit (STAT0, 14H...) will be set, and the corresponding TTIPn/TRINGn will
become high impedance if this channel is not used for remote loopback or
isnotusingMCLK totransmitinternal patterns (TAOS,AllZeros,PRBSand
in-band loopback code). When TCLKn is detected again, TCLK_LOS bit
(STAT0,14H...)willbecleared.ThereferencefrequencytodetectaTCLKn
loss is derived from MCLK.
Figure-20 TCLK Operation Flowchart
normal operation mode
transmitter n enters high
impedance status and
generates transmit clock loss
interrupt if not masked
TCLKn status?
clocked
L/H
MCLK=H/L?
all transmitters high
impedance status
yes
clocked
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT82V2048L | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:OCTAL T1/E1 SHORT HAUL ANALOG FRONT END |
| IDT82V2048LBB | 功能描述:IC LIU T1/E1 8CH SHORT 160-BGA RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:- 標準包裝:250 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| IDT82V2048LBBG | 功能描述:IC LIU T1/E1 8CH SHORT 160-BGA RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:- 標準包裝:250 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| IDT82V2048LDA | 功能描述:IC LIU T1/E1 8CH SHORT 144-TQFP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:- 標準包裝:250 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| IDT82V2048LDAG | 功能描述:IC LIU T1/E1 8CH SHORT 144-TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:- 標準包裝:250 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
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