Figure-23 Automatic Error Counter Updati" />
參數(shù)資料
型號: IDT82P20416DBFG
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 58/121頁
文件大小: 0K
描述: IC LIU T1/E1/J1 16CH SH 484BGA
標(biāo)準(zhǔn)包裝: 84
功能: 線路接口單元(LIU)
接口: E1,J1,T1
電路數(shù): 16
電源電壓: 1.8V, 3.3V
功率(瓦特): 3.10W
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 484-LFBGA
供應(yīng)商設(shè)備封裝: 484-CABGA(19x19)
包裝: 托盤
包括: AIS 警報檢測器和發(fā)生器,回送功能,PRBS 發(fā)生器 / 檢測器,遠(yuǎn)程檢測器和發(fā)生器
IDT82P20416
16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Functional Description
41
December 17, 2009
Figure-23 Automatic Error Counter Updating
3.5.6.2 Manual Error Counter Updating
When the CNT_MD bit (b1, ERR,...) is ‘0’, the Error Counter is
updated manually.
When there is a transition from ‘0’ to ‘1’ on the CNT_STOP bit (b0,
ERR,...), the Error Counter transfers the accumulated error numbers to
the ERRCH and ERRCL registers and the Error Counter will be cleared
to start a new round counting. The ERRCH and ERRCL registers should
be read in the next round of error counting, otherwise they will be over-
written.
When the ERRCH and ERRCL registers are all ‘1’s and there is still
error to be accumulated, the registers will be overflowed. The overflow is
indicated by the CNTOV_IS bit (b0, INTS2,...) and will induce an inter-
rupt reported by INT if not masked by the CNTOV_IM (b0, INTM2,...).
The process of manual Error Counter updating is illustrated in
Figure-24 Manual Error Counter Updating
Read the ERRCH & ERRCL
registers in the next second
TMOV_IS is cleared after a '1' is
written to it
Data in the Error Counter transfers
to the ERRCH & ERRCL registers
The Error Counter is cleared
One second expired?
(TMOV_IS = 1 ?)
Counting
Automatic Error Counter Updating
(CNT_MD = 1)
No
Yes
repeat the
same process
in the next
second
Read the ERRCH & ERRCL
registers in the next round
Data in the Error Counter transfers
to the ERRCH & ERRCL registers
The Error Counter is cleared
A transition from '0' to
'1' on CNT_STOP ?
Counting
Manual Error Counter Updating
(CNT_MD = 0)
No
Yes
repeat the
same
process in
the next
round
(CNT_STOP
must be
cleared
before the
next round)
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