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參數(shù)資料
| 型號： | IDT74LVCH573ASO |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | LVC/LCX/Z SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20 |
| 封裝： | 1.27 MM PITCH, SOIC-20 |
| 文件頁數(shù)： | 1/6頁 |
| 文件大?。?/td> | 111K |
| 代理商： | IDT74LVCH573ASO |
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EXTENDEDCOMMERCIALTEMPERATURERANGE
IDT74LVCH573A
3.3V CMOS OCTAL TRANSPARENT D-TYPE LATCH
APRIL 1999
1999
Integrated Device Technology, Inc.
DSC-4934/-
c
IDT74LVCH573A
ADVANCE
INFORMATION
EXTENDED COMMERCIAL TEMPERATURE RANGE
DESCRIPTION:
The LVCH573A octal transparent D-type latch is built using advanced
dual metal CMOS technology. The device features 3-state outputs de-
FEATURES:
–
0.5 MICRON CMOS Technology
–
ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
–
1.27mm pitch SOIC, 0.65mm pitch SSOP,
0.635mm pitch QSOP, 0.65mm pitch TSSOP packages
–
Extended commercial range of – 40°C to +85°C
–VCC = 3.3V ±0.3V, Normal Range
–VCC = 2.3V to 3.6V, Extended Range
–
CMOS power levels (0.4 W typ. static)
–
Rail-to-Rail output swing for increased noise margin
–
All inputs, outputs and I/O are 5 Volt tolerant
–
Supports hot insertion
3.3V CMOS OCTAL
TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS, 5 VOLT
TOLERANT I/O AND BUS-HOLD
Functional Block Diagram
OE
C1
LE
1
D
TO SEVEN OTHER CHANNELS
1
11
2
19
1
D
1
Q
signed specifically for driving highly capacitive or relatively low-impedance
loads, and is particularly suitable for implementing buffer registers, input-
output (I/O) ports, bidirectional bus drivers, and working registers.
While the latch-enable (LE) input is high, the Q outputs follow the data (D)
inputs. When LE is taken low, the Q outputs are latched at the logic levels
at the D inputs.
A buffered output-enable (
OE) input can be used to place the eight outputs
in either a normal logic state (high or low logic levels) or a high-impedance
state. In the high-impedance state, the outputs neither load nor drive the bus
lines significantly. The high-impedance state and increased drive provide
the capability to drive bus lines without interface or pullup components.
OE
does not affect the internal operations of the latch. Old data can be retained
or new data can be entered while the outputs are in the high-impedance state.
The LVCH573A has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
Inputs can be driven from either 3.3V or 5V devices. This feature allows
the use of this device as a translator in a mixed 3.3V/5V system environment.
The LVCH573A has “bus-hold” which retains the inputs’ last state
whenever the input goes to a high impedance. This prevents floating inputs
and eliminates the need for pull-up/down resistors.
Drive Features for LVCH573A:
–
High Output Drivers:
±24mA
–
Reduced system switching noise
APPLICATIONS:
5V and 3.3V mixed voltage systems
Data communication and telecommunication systems
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相關代理商/技術參數(shù) |
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