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參數(shù)資料
| 型號(hào)： | IDT74LVC86ADC |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 門電路 |
| 英文描述： | LVC/LCX/Z SERIES, QUAD 2-INPUT XOR GATE, PDSO14 |
| 封裝： | SOIC-14 |
| 文件頁(yè)數(shù)： | 1/5頁(yè) |
| 文件大?。?/td> | 57K |
| 代理商： | IDT74LVC86ADC |
INDUSTRIALTEMPERATURERANGE
IDT74LVC86A
3.3VCMOSQUADRUPLE 2-INPUT EXCLUSIVE-OR GATE
1
2
3
14
1
A
VCC
5
6
4
GND
7
13
12
10
9
11
8
1
B
1
Y
2
A
2
B
2
Y
4
B
4
A
4
Y
3
B
3
A
3
Y
OCTOBER 1999
INDUSTRIAL TEMPERATURE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
1999 Integrated Device Technology, Inc.
DSC-4725/1
FEATURES:
0.5 MICRON CMOS Technology
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
VCC = 3.3V ± 0.3V, Normal Range
VCC = 2.7V to 3.6V, Extended Range
CMOS power levels (0.4
W typ. static)
Rail-to-Rail output swing for increased noise margin
All inputs, outputs, and I/Os are 5V tolerant
Supports hot insertion
Available in SOIC, SSOP, and TSSOP packages
FUNCTIONAL BLOCK DIAGRAM
DRIVE FEATURES:
High Output Drivers: ±24mA
Reduced system switching noise
APPLICATIONS:
5V and 3.3V mixed voltage systems
Data communication and telecommunication systems
IDT74LVC86A
DESCRIPTION:
This quadruple 2-input exclusive-OR gate is built using advanced dual
metal CMOS technology. The LVC86A performs the Boolean function Y =
A B or Y = AB + AB in positive logic. A common application is as a true/
complement element. Ifoneoftheinputsislow,theotherinputisreproduced
in true form at the output. If one of the inputs is high, the signal on the other
input is reproduced inverted at the output.
The LVC86A has been designed with a ±24mA output driver. This driver
is capable of driving a moderate to heavy load while maintaining speed
performance.
Inputs can be driven from either 3.3V or 5V devices. This feature allows
the use of this device as a translator in a mixed 3.3V/5V system environ-
ment.
3.3V CMOS
QUADRUPLE 2-INPUT
EXCLUSIVE-OR GATE
WITH 5 VOLT TOLERANT I/O
SOIC/ SSOP/ TSSOP
TOP VIEW
PIN CONFIGURATION
A
B
Y
PIN DESCRIPTION
Pin Names
Description
xA, xB
DataInputs
x Y
DataOutputs
FUNCTION TABLE (EACHGATE)(1)
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
Inputs
Outputs
xA
xB
xY
LL
L
LH
H
HL
H
HH
L
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