
1
OE
1
A0
2
B3
1
A1
2
B2
1
A2
2
B1
1
A3
2
B0
GND
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
1
2
OE
VCC
1
B0
2
A3
1
B1
2
A2
1
B2
2
A1
1
B3
2
A0
P20-1
SO20-2
SO20-8
SO20-9
SO20-7
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
JANUARY 1999
1999 Integrated Device Technology, Inc.
1
DSC-3255/4
FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION:
The FST3244/32244 belong to IDT’s family of Bus switches.
Bus switch devices perform the function of connecting or iso-
lating two ports without providing any inherent current sink or
source capability. Thus they generate little or no noise of their
own while providing a low resistance path for an external driver.
OCTAL BUS SWITCH
IDT74FST3244
IDT74FST32244
Integrated Device Technology, Inc.
3255 drw 01
FEATURES:
Bus switches provide zero delay paths
Extended commercial range of –40°C to +85°C
Low switch on-resistance
TTL-compatible input and output levels
ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
Available in QSOP, TSSOP, SOIC, SSOP, and PDIP
Hot insertion capability
Very low power dissipation
These devices connect input and output ports through an n-
channel FET. When the gate-to-source junction of this FET
is adequately forward-biased, the device conducts and the
resistance between input and output ports is small. Without
adequate bias on the gate-to-source junction of the FET, the
FET is turned off, therefore with no VCC applied, the device
has not insertion capability.
The low on-resistance and simplicity of the connection be-
tween input and output ports reduces the delay in this path to
close to zero.
The FST32244 integrates terminating resistors in the de-
vice, thus eliminating the need for external 25
series resis-
tors.
The FST3244 and FST32244 are octal TTL-compatible bus
switches. The OE pins provide output enable control for all 8
bits. These devices are pin-compatible with and functionally
similar to the FCT244T.
Pin Names
Description
xOE
Output Enable Inputs (Active LOW)
xAx
A Port Bits
xBx
B Port Bits
3255 tbl 01
PIN DESCRIPTION
1
A 0
1
A 1
1
A 2
1
A 3
1
B 0
1
OE
1
B 1
1
B 2
1
B 3
2A 0
2A 1
2A 2
2A 3
2B 0
2OE
2B 1
2B 2
2B 3
PIN CONFIGURATION
3255 drw 02
DIP/SOIC/SSOP
QSOP/TSSOP
TOP VIEW